[MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards.
authorThiemo Seufer <ths@networkno.de>
Wed, 5 Sep 2007 16:44:50 +0000 (17:44 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 11 Oct 2007 22:46:03 +0000 (23:46 +0100)
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
include/asm-mips/mach-excite/cpu-feature-overrides.h
include/asm-mips/mach-sibyte/cpu-feature-overrides.h

index 07f4322c235d5b2147f2c606ccbbb115d05b5df5..107104c3cd1281ce52e4f7fabc93745f3b0c230d 100644 (file)
 #define cpu_has_nofpuex                0
 #define cpu_has_64bits         1
 
+#define cpu_has_mips32r1       0
+#define cpu_has_mips32r2       0
+#define cpu_has_mips64r1       0
+#define cpu_has_mips64r2       0
+
 #define cpu_has_inclusive_pcaches      0
 
 #define cpu_dcache_line_size() 32
index 63d5bf649af1c6aeefa0b5ba9df5cce064629a04..1c1f92415b9a28857754c5538c2efe6b41c9ac77 100644 (file)
@@ -9,7 +9,7 @@
 #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
 
 /*
- * Sibyte are MIPS64 processors weired to a specific configuration
+ * Sibyte are MIPS64 processors wired to a specific configuration
  */
 #define cpu_has_watch          1
 #define cpu_has_mips16         0
 #define cpu_has_nofpuex                0
 #define cpu_has_64bits         1
 
+#define cpu_has_mips32r1       1
+#define cpu_has_mips32r2       0
+#define cpu_has_mips64r1       1
+#define cpu_has_mips64r2       0
+
 #define cpu_has_inclusive_pcaches      0
 
 #define cpu_dcache_line_size() 32