mmc: dw_mmc: improve dw_mci_reset a bit
authorShawn Lin <shawn.lin@rock-chips.com>
Fri, 17 Feb 2017 02:59:52 +0000 (10:59 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Mon, 24 Apr 2017 19:41:06 +0000 (21:41 +0200)
Too much condition iteration makes the code
less readable. Slightly improve it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/dw_mmc.c

index 0c641fb0fe59636320f999856c8ddba98dd59a9e..d0f0f658e7418b1ba61870bbc0453db3449c7eb4 100644 (file)
@@ -1699,6 +1699,7 @@ static bool dw_mci_reset(struct dw_mci *host)
 {
        u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
        bool ret = false;
+       u32 status = 0;
 
        /*
         * Resetting generates a block interrupt, hence setting
@@ -1714,29 +1715,30 @@ static bool dw_mci_reset(struct dw_mci *host)
 
        if (dw_mci_ctrl_reset(host, flags)) {
                /*
-                * In all cases we clear the RAWINTS register to clear any
-                * interrupts.
+                * In all cases we clear the RAWINTS
+                * register to clear any interrupts.
                 */
                mci_writel(host, RINTSTS, 0xFFFFFFFF);
 
-               /* if using dma we wait for dma_req to clear */
-               if (host->use_dma) {
-                       u32 status;
-
-                       if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
-                                                     status,
-                                                     !(status & SDMMC_STATUS_DMA_REQ),
-                                                     1, 500 * USEC_PER_MSEC)) {
-                               dev_err(host->dev,
-                                       "%s: Timeout waiting for dma_req to clear during reset\n",
-                                       __func__);
-                               goto ciu_out;
-                       }
+               if (!host->use_dma) {
+                       ret = true;
+                       goto ciu_out;
+               }
 
-                       /* when using DMA next we reset the fifo again */
-                       if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
-                               goto ciu_out;
+               /* Wait for dma_req to be cleared */
+               if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
+                                             status,
+                                             !(status & SDMMC_STATUS_DMA_REQ),
+                                             1, 500 * USEC_PER_MSEC)) {
+                       dev_err(host->dev,
+                               "%s: Timeout waiting for dma_req to be cleared\n",
+                               __func__);
+                       goto ciu_out;
                }
+
+               /* when using DMA next we reset the fifo again */
+               if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
+                       goto ciu_out;
        } else {
                /* if the controller reset bit did clear, then set clock regs */
                if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {