static struct vframe_provider_s vh264mvc_vf_prov;
+static struct vdec_s *vdec = NULL;
static u32 frame_width, frame_height, frame_dur;
static u32 saved_resolution;
static struct timer_list recycle_timer;
u64 pts_us64;
u32 frame_size;
int ret = READ_VREG(MAILBOX_COMMAND);
+
+ if (is_support_no_parser()) {
+ STBUF_WRITE(&vdec->vbuf, set_rp,
+ READ_VREG(VLD_MEM_VIFIFO_RP));
+ }
/* pr_info("vh264mvc_isr, cmd =%x\n", ret); */
switch (ret & 0xff) {
case CMD_ALLOC_VIEW_0:
INIT_WORK(&error_wd_work, error_do_work);
INIT_WORK(&set_clk_work, vh264_mvc_set_clk);
+ vdec = pdata;
+
atomic_set(&vh264mvc_active, 1);
mutex_unlock(&vh264_mvc_mutex);
}
EXPORT_SYMBOL(vdec_get_frame_vdec);
+void vdec_set_vld_wp(struct vdec_s *vdec, u32 wp)
+{
+ if (vdec_single(vdec)) {
+ WRITE_VREG(VLD_MEM_VIFIFO_WP, wp);
+ }
+}
+EXPORT_SYMBOL(vdec_set_vld_wp);
+
+void vdec_config_vld_reg(struct vdec_s *vdec, u32 addr, u32 size)
+{
+ if (vdec_single(vdec)) {
+ WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 0);
+ /* reset VLD before setting all pointers */
+ WRITE_VREG(VLD_MEM_VIFIFO_WRAP_COUNT, 0);
+ /*TODO: only > m6*/
+ WRITE_VREG(DOS_SW_RESET0, (1 << 4));
+ WRITE_VREG(DOS_SW_RESET0, 0);
+
+
+ WRITE_VREG(POWER_CTL_VLD, 1 << 4);
+
+ WRITE_VREG(VLD_MEM_VIFIFO_START_PTR,
+ addr);
+ WRITE_VREG(VLD_MEM_VIFIFO_END_PTR,
+ addr + size - 8);
+ WRITE_VREG(VLD_MEM_VIFIFO_CURR_PTR,
+ addr);
+
+ WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 1);
+ WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 0);
+
+ /* set to manual mode */
+ WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 2);
+ WRITE_VREG(VLD_MEM_VIFIFO_WP, addr);
+
+ WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 3);
+ WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 2);
+
+ /* enable */
+ WRITE_VREG(VLD_MEM_VIFIFO_CONTROL,
+ (0x11 << 16) | (1<<10) | (1 << 1) | (1 << 2));
+ SET_VREG_MASK(VLD_MEM_VIFIFO_CONTROL,
+ 7 << 3);
+ }
+}
+EXPORT_SYMBOL(vdec_config_vld_reg);
+
RESERVEDMEM_OF_DECLARE(vdec, "amlogic, vdec-memory", vdec_mem_setup);
/*
uint force_hevc_clock_cntl;
void vdec_set_profile_level(struct vdec_s *vdec, u32 profile_idc, u32 level_idc);
extern void vdec_stream_skip_data(struct vdec_s *vdec, int skip_size);
+void vdec_set_vld_wp(struct vdec_s *vdec, u32 wp);
+void vdec_config_vld_reg(struct vdec_s *vdec, u32 addr, u32 size);
#endif /* VDEC_H */
v_width = READ_VREG(AV_SCRATCH_J);
v_height = READ_VREG(AV_SCRATCH_K);
+ if (is_support_no_parser()) {
+ STBUF_WRITE(&vdec->vbuf, set_rp,
+ READ_VREG(VLD_MEM_VIFIFO_RP));
+ }
+
if (v_width && v_width <= 4096
&& (v_width != vvc1_amstream_dec_info.width)) {
pr_info("frame width changed %d to %d\n",
/* def used stbuf with parser if the feature disable. */
if (!is_support_no_parser())
ops = get_esparser_stbuf_ops();
+ else if (vdec->format == VFORMAT_H264MVC ||
+ vdec->format == VFORMAT_VC1)
+ ops = get_stbuf_ops();
}
r = stream_buffer_base_init(&vdec->vbuf, ops, &pars);
}
stbuf->use_ptsserv = 1;
}
+ vdec_config_vld_reg(vdec, addr, size);
+
ret = vdec_set_input_buffer(vdec, addr, size);
if (ret) {
pr_err("[%d]: set input buffer err.\n", stbuf->id);
((stbuf->buf_start + stbuf->buf_size) - stbuf->buf_wp);
stbuf->buf_wp = val;
+ vdec_set_vld_wp(container_of(stbuf, struct vdec_s, vbuf), stbuf->buf_wp);
+
atomic_add(len, &stbuf->payload);
}