MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs
authorKevin Cernekee <cernekee@gmail.com>
Tue, 21 Oct 2014 04:27:58 +0000 (21:27 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 24 Nov 2014 06:45:11 +0000 (07:45 +0100)
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size.  If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/Kconfig

index 992f98361e5a763ab9c1bf85ff4e4c16a0c792f5..002cf4c56ebfd28b92fd16b1a8dc02b635cbf3bb 100644 (file)
@@ -1587,12 +1587,14 @@ config CPU_BMIPS4350
 
 config CPU_BMIPS4380
        bool
+       select MIPS_L1_CACHE_SHIFT_6
        select SYS_SUPPORTS_SMP
        select SYS_SUPPORTS_HOTPLUG_CPU
 
 config CPU_BMIPS5000
        bool
        select MIPS_CPU_SCACHE
+       select MIPS_L1_CACHE_SHIFT_7
        select SYS_SUPPORTS_SMP
        select SYS_SUPPORTS_HOTPLUG_CPU