sb_edac: Fix a typo and a thinko in address handling for Haswell

typo: "a7mode" chooses whether to use bits {8, 7, 9} or {8, 7, 6}
in the algorithm to spread access between memory resources. But
the non-a7mode path was incorrectly using GET_BITFIELD(addr, 7, 9)
and so picking bits {9, 8, 7}

thinko: BIT(1) of the dram_rule registers chooses whether to just
use the {8, 7, 6} (or {8, 7, 9}) bits mentioned above as they are,
or to XOR them with bits {18, 17, 16} but the code inverted the
test. We need the additional XOR when dram_rule{1} == 0.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Acked-by: Aristeu Rozanski <aris@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 1acf57ba4c86bdc95b2e6d4d8281295f5568f6fc..b9648323106b87b8de9242ca2957d248a57c82e5 100644 (file)
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -1242,9 +1242,9 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
                        bits = GET_BITFIELD(addr, 7, 8) << 1;
                        bits |= GET_BITFIELD(addr, 9, 9);
                } else
-                       bits = GET_BITFIELD(addr, 7, 9);
+                       bits = GET_BITFIELD(addr, 6, 8);
 
-               if (interleave_mode) {
+               if (interleave_mode == 0) {
                        /* interleave mode will XOR {8,7,6} with {18,17,16} */
                        idx = GET_BITFIELD(addr, 16, 18);
                        idx ^= bits;