drm/i915: Prepare for engine init unification
authorTvrtko Ursulin <tvrtko.ursulin@intel.com>
Wed, 13 Jul 2016 15:03:36 +0000 (16:03 +0100)
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>
Thu, 14 Jul 2016 10:17:02 +0000 (11:17 +0100)
Move the execlist engine setup to vfuncs so that the engine
init loop is clearly split into the mode agnostic and
specific steps.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_lrc.c

index 1eb6d4608effd519a9e14026535ce7cb5bcab889..604cfbb8aec95da723adc93acdddc9f1c1a6be76 100644 (file)
@@ -2003,6 +2003,46 @@ lrc_setup_hws(struct intel_engine_cs *engine,
        return 0;
 }
 
+static void
+logical_ring_setup(struct intel_engine_cs *engine)
+{
+       struct drm_i915_private *dev_priv = engine->i915;
+       enum forcewake_domains fw_domains;
+
+       /* Intentionally left blank. */
+       engine->buffer = NULL;
+
+       fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+                                                   RING_ELSP(engine),
+                                                   FW_REG_WRITE);
+
+       fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+                                                    RING_CONTEXT_STATUS_PTR(engine),
+                                                    FW_REG_READ | FW_REG_WRITE);
+
+       fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+                                                    RING_CONTEXT_STATUS_BUF_BASE(engine),
+                                                    FW_REG_READ);
+
+       engine->fw_domains = fw_domains;
+
+       INIT_LIST_HEAD(&engine->active_list);
+       INIT_LIST_HEAD(&engine->request_list);
+       INIT_LIST_HEAD(&engine->buffers);
+       INIT_LIST_HEAD(&engine->execlist_queue);
+       spin_lock_init(&engine->execlist_lock);
+
+       tasklet_init(&engine->irq_tasklet,
+                    intel_lrc_irq_handler, (unsigned long)engine);
+
+       logical_ring_init_platform_invariants(engine);
+       logical_ring_default_vfuncs(engine);
+       logical_ring_default_irqs(engine);
+
+       intel_engine_init_hangcheck(engine);
+       i915_gem_batch_pool_init(&dev_priv->drm, &engine->batch_pool);
+}
+
 static int
 logical_ring_init(struct intel_engine_cs *engine)
 {
@@ -2048,6 +2088,8 @@ static int logical_render_ring_init(struct intel_engine_cs *engine)
        struct drm_i915_private *dev_priv = engine->i915;
        int ret;
 
+       logical_ring_setup(engine);
+
        if (HAS_L3_DPF(dev_priv))
                engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
@@ -2084,6 +2126,13 @@ static int logical_render_ring_init(struct intel_engine_cs *engine)
        return ret;
 }
 
+static int logical_xcs_ring_init(struct intel_engine_cs *engine)
+{
+       logical_ring_setup(engine);
+
+       return logical_ring_init(engine);
+}
+
 static const struct engine_info {
        const char *name;
        unsigned exec_id;
@@ -2106,7 +2155,7 @@ static const struct engine_info {
                .guc_id = GUC_BLITTER_ENGINE,
                .mmio_base = BLT_RING_BASE,
                .irq_shift = GEN8_BCS_IRQ_SHIFT,
-               .init = logical_ring_init,
+               .init = logical_xcs_ring_init,
        },
        [VCS] = {
                .name = "bsd ring",
@@ -2114,7 +2163,7 @@ static const struct engine_info {
                .guc_id = GUC_VIDEO_ENGINE,
                .mmio_base = GEN6_BSD_RING_BASE,
                .irq_shift = GEN8_VCS1_IRQ_SHIFT,
-               .init = logical_ring_init,
+               .init = logical_xcs_ring_init,
        },
        [VCS2] = {
                .name = "bsd2 ring",
@@ -2122,7 +2171,7 @@ static const struct engine_info {
                .guc_id = GUC_VIDEO_ENGINE2,
                .mmio_base = GEN8_BSD2_RING_BASE,
                .irq_shift = GEN8_VCS2_IRQ_SHIFT,
-               .init = logical_ring_init,
+               .init = logical_xcs_ring_init,
        },
        [VECS] = {
                .name = "video enhancement ring",
@@ -2130,7 +2179,7 @@ static const struct engine_info {
                .guc_id = GUC_VIDEOENHANCE_ENGINE,
                .mmio_base = VEBOX_RING_BASE,
                .irq_shift = GEN8_VECS_IRQ_SHIFT,
-               .init = logical_ring_init,
+               .init = logical_xcs_ring_init,
        },
 };
 
@@ -2152,50 +2201,6 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
        return engine;
 }
 
-static struct intel_engine_cs *
-logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id)
-{
-       struct intel_engine_cs *engine;
-       enum forcewake_domains fw_domains;
-
-       engine = intel_engine_setup(dev_priv, id);
-
-       /* Intentionally left blank. */
-       engine->buffer = NULL;
-
-       fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
-                                                   RING_ELSP(engine),
-                                                   FW_REG_WRITE);
-
-       fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
-                                                    RING_CONTEXT_STATUS_PTR(engine),
-                                                    FW_REG_READ | FW_REG_WRITE);
-
-       fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
-                                                    RING_CONTEXT_STATUS_BUF_BASE(engine),
-                                                    FW_REG_READ);
-
-       engine->fw_domains = fw_domains;
-
-       INIT_LIST_HEAD(&engine->active_list);
-       INIT_LIST_HEAD(&engine->request_list);
-       INIT_LIST_HEAD(&engine->buffers);
-       INIT_LIST_HEAD(&engine->execlist_queue);
-       spin_lock_init(&engine->execlist_lock);
-
-       tasklet_init(&engine->irq_tasklet,
-                    intel_lrc_irq_handler, (unsigned long)engine);
-
-       logical_ring_init_platform_invariants(engine);
-       logical_ring_default_vfuncs(engine);
-       logical_ring_default_irqs(engine);
-
-       intel_engine_init_hangcheck(engine);
-       i915_gem_batch_pool_init(&dev_priv->drm, &engine->batch_pool);
-
-       return engine;
-}
-
 /**
  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
  * @dev: DRM device.
@@ -2224,7 +2229,7 @@ int intel_logical_rings_init(struct drm_device *dev)
                if (!intel_engines[i].init)
                        continue;
 
-               ret = intel_engines[i].init(logical_ring_setup(dev_priv, i));
+               ret = intel_engines[i].init(intel_engine_setup(dev_priv, i));
                if (ret)
                        goto cleanup;