Blackfin: TWI: clean up the MMR names

The standard short name for control is CTL and not CTRL.  Use TWI0_xxx
even on parts that only have one TWI bus to keep things simple.  Drop
all the cdef helpers since the bus driver takes care of everything.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 9241205fb9928a501c06f2d51aa7ebbaecb28f89..543c53da88b22a008f0a8a40e7f10140c7a0328b 100644 (file)
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -458,22 +458,22 @@
 
 /* Two-Wire Interface          (0xFFC01400 - 0xFFC014FF)                                                               */
 #define TWI0_REGBASE                   0xFFC01400
-#define TWI_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+#define TWI0_CLKDIV                    0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                   0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL         0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT                0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR                0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL                0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT               0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR               0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT          0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK          0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL          0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT         0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8         0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16                0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8         0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16                0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
 
 
 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                                */
@@ -1319,7 +1319,7 @@
 #define        TWI_ENA         0x0080          /* TWI Enable                                                                   */
 #define        SCCB            0x0200          /* SCCB Compatibility Enable                                    */
 
-/* TWI_SLAVE_CTRL Masks                                                                                                                        */
+/* TWI_SLAVE_CTL Masks                                                                                                                 */
 #define        SEN                     0x0001          /* Slave Enable                                                                 */
 #define        SADD_LEN        0x0002          /* Slave Address Length                                                 */
 #define        STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
@@ -1330,7 +1330,7 @@
 #define        SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
 #define GCALL          0x0002          /* General Call Indicator                                               */
 
-/* TWI_MASTER_CTRL Masks                                                                                                       */
+/* TWI_MASTER_CTL Masks                                                                                                        */
 #define        MEN                     0x0001          /* Master Mode Enable                                           */
 #define        MADD_LEN        0x0002          /* Master Address Length                                        */
 #define        MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */

diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 620834097632d4457009da0de910afadfa70c8a7..f08dae0d513879ef82c61541817c2392f041fd83 100644 (file)
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -458,22 +458,22 @@
 
 /* Two-Wire Interface          (0xFFC01400 - 0xFFC014FF)                                                               */
 #define TWI0_REGBASE                   0xFFC01400
-#define TWI_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+#define TWI0_CLKDIV                    0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                   0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL         0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT                0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR                0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL                0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT               0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR               0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT          0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK          0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL          0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT         0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8         0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16                0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8         0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16                0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
 
 
 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                                */
@@ -1328,7 +1328,7 @@
 #define        TWI_ENA         0x0080          /* TWI Enable                                                                   */
 #define        SCCB            0x0200          /* SCCB Compatibility Enable                                    */
 
-/* TWI_SLAVE_CTRL Masks                                                                                                                        */
+/* TWI_SLAVE_CTL Masks                                                                                                                 */
 #define        SEN                     0x0001          /* Slave Enable                                                                 */
 #define        SADD_LEN        0x0002          /* Slave Address Length                                                 */
 #define        STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
@@ -1339,7 +1339,7 @@
 #define        SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
 #define GCALL          0x0002          /* General Call Indicator                                               */
 
-/* TWI_MASTER_CTRL Masks                                                                                                       */
+/* TWI_MASTER_CTL Masks                                                                                                        */
 #define        MEN                     0x0001          /* Master Mode Enable                                           */
 #define        MADD_LEN        0x0002          /* Master Address Length                                        */
 #define        MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */

diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index cf396ea40092a010344554f469a418160b37a1e0..aad61b8873731f5ed6877e189ab61bf4e2a85dfa 100644 (file)
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -434,22 +434,22 @@
 
 /* Two-Wire Interface          (0xFFC01400 - 0xFFC014FF)                                                               */
 #define TWI0_REGBASE                   0xFFC01400
-#define TWI_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+#define TWI0_CLKDIV                    0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                   0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL         0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT                0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR                0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL                0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT               0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR               0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT          0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK          0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL          0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT         0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8         0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16                0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8         0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16                0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
 
 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                                */
 #define PORTGIO                                        0xFFC01500      /* Port G I/O Pin State Specify Register                                */
@@ -1642,7 +1642,7 @@
 #define        TWI_ENA         0x0080  /* TWI Enable                                                                   */
 #define        SCCB            0x0200  /* SCCB Compatibility Enable                                    */
 
-/* TWI_SLAVE_CTRL Masks                                                                                                                        */
+/* TWI_SLAVE_CTL Masks                                                                                                                 */
 #define        SEN                     0x0001  /* Slave Enable                                                                 */
 #define        SADD_LEN        0x0002  /* Slave Address Length                                                 */
 #define        STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
@@ -1653,7 +1653,7 @@
 #define        SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
 #define GCALL          0x0002  /* General Call Indicator                                               */
 
-/* TWI_MASTER_CTRL Masks                                                                                                       */
+/* TWI_MASTER_CTL Masks                                                                                                        */
 #define        MEN                     0x0001  /* Master Mode Enable                                           */
 #define        MADD_LEN        0x0002  /* Master Address Length                                        */
 #define        MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */

diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 401ebd79d0aae74f3a5b70fcc21183fe406e9174..66aa722cf6c89beb302816ab44f039ad35418dd3 100644 (file)
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -1293,70 +1293,6 @@
 #define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
 #define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTRL()    bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL()    bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
 #define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
 #define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
 #define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)

diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index d7061d9f2a832cd2c0936edf06db800d03a62637..b674a1c4aef1efdbe30eb6c1cb5ca76d2bd260f6 100644 (file)
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -442,15 +442,15 @@
 /* Two-Wire Interface 0        (0xFFC01400 - 0xFFC014FF)                        */
 #define        TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register */
 #define        TWI0_CONTROL            0xFFC01404      /* TWI0 Master Internal Time Reference Register */
-#define        TWI0_SLAVE_CTRL         0xFFC01408      /* Slave Mode Control Register */
+#define        TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register */
 #define        TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register */
 #define        TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register */
-#define        TWI0_MASTER_CTRL        0xFFC01414      /* Master Mode Control Register */
+#define        TWI0_MASTER_CTL 0xFFC01414      /* Master Mode Control Register */
 #define        TWI0_MASTER_STAT        0xFFC01418      /* Master Mode Status Register */
 #define        TWI0_MASTER_ADDR        0xFFC0141C      /* Master Mode Address Register */
 #define        TWI0_INT_STAT           0xFFC01420      /* TWI0 Master Interrupt Register */
 #define        TWI0_INT_MASK           0xFFC01424      /* TWI0 Master Interrupt Mask Register */
-#define        TWI0_FIFO_CTRL          0xFFC01428      /* FIFO Control Register */
+#define        TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register */
 #define        TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register */
 #define        TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register */
 #define        TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register */
@@ -761,15 +761,15 @@
 /* Two-Wire Interface 1        (0xFFC02200 - 0xFFC022FF)                        */
 #define        TWI1_CLKDIV                     0xFFC02200      /* Serial Clock Divider Register */
 #define        TWI1_CONTROL            0xFFC02204      /* TWI1 Master Internal Time Reference Register */
-#define        TWI1_SLAVE_CTRL         0xFFC02208      /* Slave Mode Control Register */
+#define        TWI1_SLAVE_CTL          0xFFC02208      /* Slave Mode Control Register */
 #define        TWI1_SLAVE_STAT         0xFFC0220C      /* Slave Mode Status Register */
 #define        TWI1_SLAVE_ADDR         0xFFC02210      /* Slave Mode Address Register */
-#define        TWI1_MASTER_CTRL        0xFFC02214      /* Master Mode Control Register */
+#define        TWI1_MASTER_CTL 0xFFC02214      /* Master Mode Control Register */
 #define        TWI1_MASTER_STAT        0xFFC02218      /* Master Mode Status Register */
 #define        TWI1_MASTER_ADDR        0xFFC0221C      /* Master Mode Address Register */
 #define        TWI1_INT_STAT           0xFFC02220      /* TWI1 Master Interrupt Register */
 #define        TWI1_INT_MASK           0xFFC02224      /* TWI1 Master Interrupt Mask Register */
-#define        TWI1_FIFO_CTRL          0xFFC02228      /* FIFO Control Register */
+#define        TWI1_FIFO_CTL           0xFFC02228      /* FIFO Control Register */
 #define        TWI1_FIFO_STAT          0xFFC0222C      /* FIFO Status Register */
 #define        TWI1_XMT_DATA8          0xFFC02280      /* FIFO Transmit Data Single Byte Register */
 #define        TWI1_XMT_DATA16         0xFFC02284      /* FIFO Transmit Data Double Byte Register */
@@ -2401,7 +2401,7 @@
 #define        XMTSERV         0x0040          /* Transmit FIFO Service */
 #define        RCVSERV         0x0080          /* Receive FIFO Service */
 
-/* TWIx_FIFO_CTRL Masks                                         */
+/* TWIx_FIFO_CTL Masks                                  */
 #define        XMTFLUSH        0x0001          /* Transmit Buffer Flush */
 #define        RCVFLUSH        0x0002          /* Receive Buffer Flush */
 #define        XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */

diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index f916c52a148afded7f39137e474ef27a0466824c..e2771094de0286adf016363e2447f3a793dd3ed0 100644 (file)
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -60,15 +60,15 @@
 #define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
 #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
 #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
 #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
 #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
 #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
 #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
 #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
 #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */

diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 72c343646b2a46e4c17ef4876fa92d45150dbf90..3d131065f8e6b8868a794a604fbeed7b8ee32be8 100644 (file)
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
 #define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
 #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
 #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
 #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
 #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
 #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
 #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
 #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
 #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */

diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 54143441af5ede0d8ee7107531b4aad6850a8d05..01d52fade45e044c7a0d331925f6c875416f6caf 100644 (file)
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -105,15 +105,15 @@
 #define                     TWI0_REGBASE  0xffc00700
 #define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
 #define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
-#define                  TWI0_SLAVE_CTRL  0xffc00708   /* TWI Slave Mode Control Register */
+#define                   TWI0_SLAVE_CTL  0xffc00708   /* TWI Slave Mode Control Register */
 #define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
 #define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
-#define                 TWI0_MASTER_CTRL  0xffc00714   /* TWI Master Mode Control Register */
+#define                  TWI0_MASTER_CTL  0xffc00714   /* TWI Master Mode Control Register */
 #define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
 #define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
 #define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
 #define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
-#define                   TWI0_FIFO_CTRL  0xffc00728   /* TWI FIFO Control Register */
+#define                    TWI0_FIFO_CTL  0xffc00728   /* TWI FIFO Control Register */
 #define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
 #define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */