#define _PREFETCH_ENABLE (0x1 << 1)
#define _PREFETCH_DISABLE (0x0 << 1)
+#define _PORT_MASK(pmask) ((pmask) << 16)
+
/*
* Use below definitions for TLB properties setting.
*
(_PRIVATE_WAY_ADDR | _TARGET_READWRITE | _PREFETCH_DISABLE)
#define SYSMMU_PRIV_ADDR_PREFETCH_ASCENDING_READ \
(_PRIVATE_WAY_ADDR | _TARGET_READ | _DIR_ASCENDING | _PREFETCH_ENABLE)
+
+/* PORT_TYPE_DEFINE: Definition for TLB port dedication "configuration". */
+#define SYSMMU_PORT_NO_PREFETCH_READ(pmask) \
+ ( _PORT_MASK(pmask) | _TARGET_READ | _PREFETCH_DISABLE)
+#define SYSMMU_PORT_NO_PREFETCH_WRITE(pmask) \
+ ( _PORT_MASK(pmask) | _TARGET_WRITE | _PREFETCH_DISABLE)
+#define SYSMMU_PORT_NO_PREFETCH_READWRITE(pmask) \
+ ( _PORT_MASK(pmask) | _TARGET_READWRITE | _PREFETCH_DISABLE)
+#define SYSMMU_PORT_PREFETCH_PREDICTION_READ(pmask) \
+ ( _PORT_MASK(pmask) | _TARGET_READ | _DIR_PREDICTION | _PREFETCH_ENABLE)
+#define SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(pmask) \
+ ( _PORT_MASK(pmask) | _TARGET_WRITE | _DIR_PREDICTION | _PREFETCH_ENABLE)
+
#endif /* _DT_BINDINGS_EXYNOS_SYSTEM_MMU_H */