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ARM: dts: STiH410-family: fix wrong parent clock frequency
authorPatrice Chotard <patrice.chotard@st.com>
Fri, 6 Jan 2017 13:30:21 +0000 (14:30 +0100)
committerPatrice Chotard <patrice.chotard@st.com>
Thu, 12 Jan 2017 16:18:03 +0000 (17:18 +0100)
The clock parent was lower than child clock which is not correct.
In some use case, it leads to division by zero.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
arch/arm/boot/dts/stih410.dtsi patch | blob | blame | history

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 8be99d010fb392bf4a34b94272ac6e29d01fbcad..3c9672c5b09f0a5f904859d34205c49d7134804d 100644 (file)
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -131,7 +131,7 @@
                                                 <&clk_s_d2_quadfs 0>;
 
                        assigned-clock-rates = <297000000>,
-                                              <108000000>,
+                                              <297000000>,
                                               <0>,
                                               <400000000>,
                                               <400000000>;