projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: d65fae9)
[media] v4l: vsp1: Add tri-planar memory formats support
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Thu, 12 Nov 2015 00:04:24 +0000 (22:04 -0200)
committerMauro Carvalho Chehab <mchehab@osg.samsung.com>
Fri, 19 Feb 2016 10:10:37 +0000 (08:10 -0200)
Tri-planar memory formats store the Y, U and V components in separate
planes. The VSP hardware supports them, the driver now does too.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
drivers/media/platform/vsp1/vsp1_video.c patch | blob | blame | history

diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c
index b4dca57d1ae3f6d78a3417251089939a7da15f77..ac07dd8e4a8137ef2c1d5cea323f7488c7bb09c1 100644 (file)
--- a/drivers/media/platform/vsp1/vsp1_video.c
+++ b/drivers/media/platform/vsp1/vsp1_video.c
@@ -130,6 +130,26 @@ static const struct vsp1_format_info vsp1_video_formats[] = {
          VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
          VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
          3, { 8, 8, 8 }, false, false, 2, 2, false },
+       { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
+         VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
+         VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
+         3, { 8, 8, 8 }, false, true, 2, 2, false },
+       { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
+         VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
+         VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
+         3, { 8, 8, 8 }, false, false, 2, 1, false },
+       { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
+         VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
+         VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
+         3, { 8, 8, 8 }, false, true, 2, 1, false },
+       { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
+         VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
+         VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
+         3, { 8, 8, 8 }, false, false, 1, 1, false },
+       { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
+         VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
+         VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
+         3, { 8, 8, 8 }, false, true, 1, 1, false },
 };
 
 /*