static int
nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
{
- struct nvkm_therm *therm = nvkm_therm(clk);
- struct nvkm_volt *volt = nvkm_volt(clk);
+ struct nvkm_subdev *subdev = &clk->subdev;
+ struct nvkm_device *device = subdev->device;
+ struct nvkm_therm *therm = device->therm;
+ struct nvkm_volt *volt = device->volt;
struct nvkm_cstate *cstate;
int ret;
if (therm) {
ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
if (ret && ret != -ENODEV) {
- nv_error(clk, "failed to raise fan speed: %d\n", ret);
+ nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
return ret;
}
}
if (volt) {
ret = volt->set_id(volt, cstate->voltage, +1);
if (ret && ret != -ENODEV) {
- nv_error(clk, "failed to raise voltage: %d\n", ret);
+ nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
return ret;
}
}
if (volt) {
ret = volt->set_id(volt, cstate->voltage, -1);
if (ret && ret != -ENODEV)
- nv_error(clk, "failed to lower voltage: %d\n", ret);
+ nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
}
if (therm) {
ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
if (ret && ret != -ENODEV)
- nv_error(clk, "failed to lower fan speed: %d\n", ret);
+ nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
}
return ret;
static int
nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
{
- struct nvkm_fb *fb = nvkm_fb(clk);
+ struct nvkm_subdev *subdev = &clk->subdev;
+ struct nvkm_fb *fb = subdev->device->fb;
struct nvkm_pstate *pstate;
int ret, idx = 0;
break;
}
- nv_debug(clk, "setting performance state %d\n", pstatei);
+ nvkm_debug(subdev, "setting performance state %d\n", pstatei);
clk->pstate = pstatei;
if (fb->ram && fb->ram->calc) {
nvkm_pstate_work(struct work_struct *work)
{
struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
+ struct nvkm_subdev *subdev = &clk->subdev;
int pstate;
if (!atomic_xchg(&clk->waiting, 0))
return;
clk->pwrsrc = power_supply_is_system_supplied();
- nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
- clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
- clk->astate, clk->tstate, clk->dstate);
+ nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
+ clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
+ clk->astate, clk->tstate, clk->dstate);
pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
if (clk->state_nr && pstate != -1) {
pstate = clk->pstate = -1;
}
- nv_trace(clk, "-> %d\n", pstate);
+ nvkm_trace(subdev, "-> %d\n", pstate);
if (pstate != clk->pstate) {
int ret = nvkm_pstate_prog(clk, pstate);
if (ret) {
- nv_error(clk, "error setting pstate %d: %d\n",
- pstate, ret);
+ nvkm_error(subdev, "error setting pstate %d: %d\n",
+ pstate, ret);
}
}
{
struct nvkm_domain *clock = clk->domains - 1;
struct nvkm_cstate *cstate;
+ struct nvkm_subdev *subdev = &clk->subdev;
char info[3][32] = { "", "", "" };
char name[4] = "--";
int i = -1;
if (hi == 0)
continue;
- nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
+ nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
list_for_each_entry(cstate, &pstate->list, head) {
u32 freq = cstate->domain[clock->name];
lo = min(lo, freq);
hi = max(hi, freq);
- nv_debug(clk, "%10d KHz\n", freq);
+ nvkm_debug(subdev, "%10d KHz\n", freq);
}
if (clock->mname && ++i < ARRAY_SIZE(info)) {
}
}
- nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
+ nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
}
static void
_nvkm_clk_init(struct nvkm_object *object)
{
struct nvkm_clk *clk = (void *)object;
+ struct nvkm_subdev *subdev = &clk->subdev;
struct nvkm_domain *clock = clk->domains;
int ret;
while (clock->name != nv_clk_src_max) {
ret = clk->read(clk, clock->name);
if (ret < 0) {
- nv_error(clk, "%02x freq unknown\n", clock->name);
+ nvkm_error(subdev, "%02x freq unknown\n", clock->name);
return ret;
}
clk->bstate.base.domain[clock->name] = ret;
gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
switch (src) {
case nv_clk_src_crystal:
case nv_clk_src_vdec:
return read_clk(clk, 0x0e);
default:
- nv_error(clk, "invalid clock source %d\n", src);
+ nvkm_error(subdev, "invalid clock source %d\n", src);
return -EINVAL;
}
}
gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
switch (src) {
case nv_clk_src_crystal:
case nv_clk_src_vdec:
return read_clk(clk, 0x0e);
default:
- nv_error(clk, "invalid clock source %d\n", src);
+ nvkm_error(subdev, "invalid clock source %d\n", src);
return -EINVAL;
}
}
static int
gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
{
+ struct nvkm_subdev *subdev = &clk->base.subdev;
u32 target_clk_f, ref_clk_f, target_freq;
u32 min_vco_f, max_vco_f;
u32 low_pl, high_pl, best_pl;
}
}
- nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
- pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
+ nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
+ pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
/* Select lowest possible VCO */
for (pl = low_pl; pl <= high_pl; pl++) {
WARN_ON(best_delta == ~0);
if (best_delta != 0)
- nv_debug(clk, "no best match for target @ %dMHz on gpc_pll",
- target_clk_f);
+ nvkm_debug(subdev,
+ "no best match for target @ %dMHz on gpc_pll",
+ target_clk_f);
clk->m = best_m;
clk->n = best_n;
target_freq = gk20a_pllg_calc_rate(clk) / MHZ;
- nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
- target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]);
+ nvkm_debug(subdev,
+ "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
+ target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]);
return 0;
}
static int
gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
{
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 val;
int ramp_timeout;
nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
if (ramp_timeout <= 0) {
- nv_error(clk, "gpcpll dynamic ramp timeout\n");
+ nvkm_error(subdev, "gpcpll dynamic ramp timeout\n");
return -ETIMEDOUT;
}
static int
_gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
{
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 val, cfg;
u32 m_old, pl_old, n_lo;
_gk20a_pllg_disable(clk);
- nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n,
- clk->pl);
+ nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
+ clk->m, clk->n, clk->pl);
n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco,
clk->parent_rate / MHZ);
gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct gk20a_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
switch (src) {
case nv_clk_src_crystal:
gk20a_pllg_read_mnp(clk);
return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
default:
- nv_error(clk, "invalid clock source %d\n", src);
+ nvkm_error(subdev, "invalid clock source %d\n", src);
return -EINVAL;
}
}
gk20a_clk_init(struct nvkm_object *object)
{
struct gk20a_clk *clk = (void *)object;
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
int ret;
nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
ret = gk20a_clk_prog(&clk->base);
if (ret) {
- nv_error(clk, "cannot initialize clock\n");
+ nvkm_error(subdev, "cannot initialize clock\n");
return ret;
}
plat = nv_device_to_platform(nv_device(parent));
clk->parent_rate = clk_get_rate(plat->gpu->clk);
- nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ);
+ nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n",
+ clk->parent_rate / MHZ);
clk->base.read = gk20a_clk_read;
clk->base.calc = gk20a_clk_calc;
gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct gt215_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 hsrc;
switch (src) {
case 3:
return 277000;
default:
- nv_error(clk, "unknown HOST clock source %d\n", hsrc);
+ nvkm_error(subdev, "unknown HOST clock source %d\n", hsrc);
return -EINVAL;
}
default:
- nv_error(clk, "invalid clock source %d\n", src);
+ nvkm_error(subdev, "invalid clock source %d\n", src);
return -EINVAL;
}
mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct mcp77_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 mast = nvkm_rd32(device, 0x00c054);
u32 P = 0;
break;
}
- nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
+ nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
return 0;
}
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
+ struct nvkm_subdev *subdev = &clk->base.subdev;
u32 out = 0, clock = 0;
int N, M, P1, P2 = 0;
int divs = 0;
}
/* Print strategy! */
- nv_debug(clk, "nvpll: %08x %08x %08x\n",
- clk->ccoef, clk->cpost, clk->cctrl);
- nv_debug(clk, " spll: %08x %08x %08x\n",
- clk->scoef, clk->spost, clk->sctrl);
- nv_debug(clk, " vdiv: %08x\n", clk->vdiv);
+ nvkm_debug(subdev, "nvpll: %08x %08x %08x\n",
+ clk->ccoef, clk->cpost, clk->cctrl);
+ nvkm_debug(subdev, " spll: %08x %08x %08x\n",
+ clk->scoef, clk->spost, clk->sctrl);
+ nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv);
if (clk->csrc == nv_clk_src_hclkm4)
- nv_debug(clk, "core: hrefm4\n");
+ nvkm_debug(subdev, "core: hrefm4\n");
else
- nv_debug(clk, "core: nvpll\n");
+ nvkm_debug(subdev, "core: nvpll\n");
if (clk->ssrc == nv_clk_src_hclkm4)
- nv_debug(clk, "shader: hrefm4\n");
+ nvkm_debug(subdev, "shader: hrefm4\n");
else if (clk->ssrc == nv_clk_src_core)
- nv_debug(clk, "shader: nvpll\n");
+ nvkm_debug(subdev, "shader: nvpll\n");
else
- nv_debug(clk, "shader: spll\n");
+ nvkm_debug(subdev, "shader: spll\n");
if (clk->vsrc == nv_clk_src_hclkm4)
- nv_debug(clk, "vdec: 500MHz\n");
+ nvkm_debug(subdev, "vdec: 500MHz\n");
else
- nv_debug(clk, "vdec: core\n");
+ nvkm_debug(subdev, "vdec: core\n");
return 0;
}
mcp77_clk_prog(struct nvkm_clk *obj)
{
struct mcp77_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 pllmask = 0, mast;
unsigned long flags;
unsigned long *f = &flags;
mast |= 0x00000003;
break;
default:
- nv_warn(clk,"Reclocking failed: unknown core clock\n");
+ nvkm_warn(subdev, "Reclocking failed: unknown core clock\n");
goto resume;
}
mast |= 0x00000030;
break;
default:
- nv_warn(clk,"Reclocking failed: unknown sclk clock\n");
+ nvkm_warn(subdev, "Reclocking failed: unknown sclk clock\n");
goto resume;
}
nv40_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct nv40_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 mast = nvkm_rd32(device, 0x00c040);
switch (src) {
break;
}
- nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
+ nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
return -EINVAL;
}
static u32
read_pll_src(struct nv50_clk *clk, u32 base)
{
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 coef, ref = clk->base.read(&clk->base, nv_clk_src_crystal);
u32 rsel = nvkm_rd32(device, 0x00e18c);
int P, N, M, id;
case 0x4008: id = !!(rsel & 0x00000008); break;
case 0x4030: id = 0; break;
default:
- nv_error(clk, "ref: bad pll 0x%06x\n", base);
+ nvkm_error(subdev, "ref: bad pll %06x\n", base);
return 0;
}
case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
case 0x4030: rsel = 3; break;
default:
- nv_error(clk, "ref: bad pll 0x%06x\n", base);
+ nvkm_error(subdev, "ref: bad pll %06x\n", base);
return 0;
}
static u32
read_pll_ref(struct nv50_clk *clk, u32 base)
{
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 src, mast = nvkm_rd32(device, 0x00c040);
switch (base) {
case 0x00e810:
return clk->base.read(&clk->base, nv_clk_src_crystal);
default:
- nv_error(clk, "bad pll 0x%06x\n", base);
+ nvkm_error(subdev, "bad pll %06x\n", base);
return 0;
}
nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
{
struct nv50_clk *clk = container_of(obj, typeof(*clk), base);
- struct nvkm_device *device = clk->base.subdev.device;
+ struct nvkm_subdev *subdev = &clk->base.subdev;
+ struct nvkm_device *device = subdev->device;
u32 mast = nvkm_rd32(device, 0x00c040);
u32 P = 0;
break;
}
- nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
+ nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
return -EINVAL;
}
}
if (unlikely(best_err == ~0)) {
- nv_error(subdev, "unable to find matching pll values\n");
+ nvkm_error(subdev, "unable to find matching pll values\n");
return -EINVAL;
}
}
if (!ret)
- nv_error(subdev, "unable to compute acceptable pll values\n");
+ nvkm_error(subdev, "unable to compute acceptable pll values\n");
return ret;
}
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff