}
return 0;
}
-device_initcall(beagle_opp_init);
+omap_device_initcall(beagle_opp_init);
static void __init omap3_beagle_init(void)
{
#include <video/omapdss.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
+#include "soc.h"
#include "board-rx51.h"
#include "mux.h"
return 0;
}
-subsys_initcall(rx51_video_init);
+omap_subsys_initcall(rx51_video_init);
#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
return ret;
}
-arch_initcall(omap2xxx_clk_arch_init);
+omap_arch_initcall(omap2xxx_clk_arch_init);
return ret;
}
-arch_initcall(omap3xxx_clk_arch_init);
+omap_arch_initcall(omap3xxx_clk_arch_init);
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
-postcore_initcall(omap3_l3_init);
+omap_postcore_initcall(omap3_l3_init);
static int __init omap4_l3_init(void)
{
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
-postcore_initcall(omap4_l3_init);
+omap_postcore_initcall(omap4_l3_init);
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
return 0;
}
-arch_initcall(omap2_init_devices);
+omap_arch_initcall(omap2_init_devices);
return omap_hwmod_for_each_by_class("dma",
omap2_system_dma_init_dev, NULL);
}
-arch_initcall(omap2_system_dma_init);
+omap_arch_initcall(omap2_system_dma_init);
}
-arch_initcall(omap_init_drm);
+omap_arch_initcall(omap_init_drm);
#endif
return 0;
}
-subsys_initcall(emu_init);
+omap_subsys_initcall(emu_init);
return 0;
}
-arch_initcall(omap_init_vrfb);
+omap_arch_initcall(omap_init_vrfb);
#endif
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
return platform_device_register(&omap_fb_device);
}
-arch_initcall(omap_init_fb);
+omap_arch_initcall(omap_init_fb);
#endif
#include <linux/of.h>
#include <linux/platform_data/gpio-omap.h>
+#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
/*
* gpio_init needs to be done before
* machine_init functions access gpio APIs.
- * Hence gpio_init is a postcore_initcall.
+ * Hence gpio_init is a omap_postcore_initcall.
*/
static int __init omap2_gpio_init(void)
{
return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
}
-postcore_initcall(omap2_gpio_init);
+omap_postcore_initcall(omap2_gpio_init);
}
-postcore_initcall(gpmc_init);
+omap_postcore_initcall(gpmc_init);
module_exit(gpmc_exit);
static int __init omap_gpmc_init(void)
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
}
-postcore_initcall(omap_gpmc_init);
+omap_postcore_initcall(omap_gpmc_init);
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
{
#include <linux/err.h>
#include <linux/platform_device.h>
+#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "hdq1w.h"
return 0;
}
-arch_initcall(omap_init_hdq);
+omap_arch_initcall(omap_init_hdq);
return retval;
}
/* early board code might need to reserve specific hwspinlock instances */
-postcore_initcall(hwspinlocks_init);
+omap_postcore_initcall(hwspinlocks_init);
#include <linux/omap-dma.h>
+#include "soc.h"
#include "omap_device.h"
/*
return 0;
}
-arch_initcall(omap2_mcbsp_init);
+omap_arch_initcall(omap2_mcbsp_init);
return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
}
/* must be ready before omap3isp is probed */
-subsys_initcall(omap_iommu_init);
+omap_subsys_initcall(omap_iommu_init);
static void __exit omap_iommu_exit(void)
{
#include <linux/clk.h>
#include <linux/io.h>
+#include "soc.h"
#include "common.h"
#include "prm2xxx.h"
return 0;
}
-core_initcall(omap2xxx_common_look_up_clks_for_reset);
+omap_core_initcall(omap2xxx_common_look_up_clks_for_reset);
return 0;
}
-early_initcall(omap_l2_cache_init);
+omap_early_initcall(omap_l2_cache_init);
#endif
void __iomem *omap4_get_sar_ram_base(void)
return 0;
}
-early_initcall(omap4_sar_ram_init);
+omap_early_initcall(omap4_sar_ram_init);
static struct of_device_id irq_match[] __initdata = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
#include <linux/of.h>
#include <linux/notifier.h>
+#include "soc.h"
#include "omap_device.h"
#include "omap_hwmod.h"
bus_register_notifier(&platform_bus_type, &platform_nb);
return 0;
}
-core_initcall(omap_device_init);
+omap_core_initcall(omap_device_init);
/**
* omap_device_late_idle - idle devices without drivers
bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
return 0;
}
-late_initcall(omap_device_late_init);
+omap_late_initcall(omap_device_late_init);
return 0;
}
-core_initcall(omap_hwmod_setup_all);
+omap_core_initcall(omap_hwmod_setup_all);
/**
* omap_hwmod_enable - enable an omap_hwmod
return 0;
}
-early_initcall(omap4430_phy_power_down);
+omap_early_initcall(omap4430_phy_power_down);
void am35x_musb_reset(void)
{
return r;
}
-device_initcall(omap3_opp_init);
+omap_device_initcall(omap3_opp_init);
ARRAY_SIZE(omap446x_opp_def_list));
return r;
}
-device_initcall(omap4_opp_init);
+omap_device_initcall(omap4_opp_init);
return 0;
}
-arch_initcall(pm_dbg_init);
+omap_arch_initcall(pm_dbg_init);
#endif
return 0;
}
-postcore_initcall(omap2_common_pm_init);
+omap_postcore_initcall(omap2_common_pm_init);
int __init omap2_common_pm_late_init(void)
{
return omap2_init_pmu(oh_num, oh_names);
}
-subsys_initcall(omap_init_pmu);
+omap_subsys_initcall(omap_init_pmu);
return ret;
}
-subsys_initcall(omap3xxx_prm_late_init);
+omap_subsys_initcall(omap3xxx_prm_late_init);
static void __exit omap3xxx_prm_exit(void)
{
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
}
-subsys_initcall(omap44xx_prm_late_init);
+omap_subsys_initcall(omap44xx_prm_late_init);
static void __exit omap44xx_prm_exit(void)
{
return 0;
}
-core_initcall(omap_serial_early_init);
+omap_core_initcall(omap_serial_early_init);
/**
* omap_serial_init_port() - initialize single serial port
pr_info("SmartReflex Class3 initialized\n");
return sr_register_class(&class3_data);
}
-late_initcall(sr_class3_init);
+omap_late_initcall(sr_class3_init);
return 0;
}
-arch_initcall(omap2_dm_timer_init);
+omap_arch_initcall(omap2_dm_timer_init);
/**
* omap2_override_clocksource - clocksource override with user configuration
dev_name, oh->name);
return 0;
}
-subsys_initcall(omap_init_wdt);
+omap_subsys_initcall(omap_init_wdt);