tg3: Assign correct tx margin for 5719
authorMatt Carlson <mcarlson@broadcom.com>
Wed, 24 Nov 2010 08:31:46 +0000 (08:31 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 24 Nov 2010 19:06:16 +0000 (11:06 -0800)
Commit d309a46e42542223946d3a9e4e239fdc945cb53e, entitled
"tg3: 5719: Prevent tx data corruption", was supposed to contain the tx
margin adjustment but it looks like it somehow was omitted.  This patch
fixes the problem.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/tg3.c
drivers/net/tg3.h

index ca6b3cbf44d5a160d4eedca0def96e442ecb2042..4dc07564e1412535c7f21cf651d1209b9c1cf586 100644 (file)
@@ -8206,6 +8206,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
            (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                val = tr32(TG3_RDMA_RSRVCTRL_REG);
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                       val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
+                       val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
+               }
                tw32(TG3_RDMA_RSRVCTRL_REG,
                     val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
        }
index 4a1974804b9fcd0c6531c86f899c03834d0061db..06a4e7e8fff395d9041487b3c249d33728b9efee 100644 (file)
 
 #define TG3_RDMA_RSRVCTRL_REG          0x00004900
 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX         0x00000004
+#define TG3_RDMA_RSRVCTRL_TXMRGN_320B   0x28000000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK   0xffe00000
 /* 0x4904 --> 0x4910 unused */
 
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL     0x00004910