clk: sunxi-ng: Fix fractional mode for N-M clocks

N-M factor clock driver is missing a call to ccu_frac_helper_enable()
when fractional mode is used. Additionally, most SoCs require that M
factor must be set to 0 when fractional mode is used.

Without this patch, clock keeps the old value and clk_set_rate() returns
without error.

Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 5e5e90a4a50c8bd80a9ca0ea1fc91ccee9a3428e..c6ba866b99d3c0078bb5c25a337fc9ca9e4abf35 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -117,10 +117,22 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
        unsigned long flags;
        u32 reg;
 
-       if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
+       if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
+               spin_lock_irqsave(nm->common.lock, flags);
+
+               /* most SoCs require M to be 0 if fractional mode is used */
+               reg = readl(nm->common.base + nm->common.reg);
+               reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
+               writel(reg, nm->common.base + nm->common.reg);
+
+               spin_unlock_irqrestore(nm->common.lock, flags);
+
+               ccu_frac_helper_enable(&nm->common, &nm->frac);
+
                return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate);
-       else
+       } else {
                ccu_frac_helper_disable(&nm->common, &nm->frac);
+       }
 
        _nm.min_n = nm->n.min ?: 1;
        _nm.max_n = nm->n.max ?: 1 << nm->n.width;