clk: imx7d: Fix the DDR PLL enable bit

Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 0039b169364ec9d70b3bfac9f067af11c02d9643..9af62ee8f347af29bfd474c0475957aa2da85c8a 100644 (file)
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -453,7 +453,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                ops = &clk_pllv3_enet_ops;
                break;
        case IMX_PLLV3_DDR_IMX7:
-               pll->power_bit = IMX7_ENET_PLL_POWER;
+               pll->power_bit = IMX7_DDR_PLL_POWER;
                ops = &clk_pllv3_av_ops;
                break;
        default: