clk / highbank: Prevent glitches in non-bypass reset mode

The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 52fecadf004a11c2fb597d90ad39d9ef4c9342ab..3a0b723da2bc3ff70f735cdb43048c2e3bfc41eb 100644 (file)
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
                reg |= HB_PLL_EXT_ENA;
                reg &= ~HB_PLL_EXT_BYPASS;
        } else {
+               writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
                reg &= ~HB_PLL_DIVQ_MASK;
                reg |= divq << HB_PLL_DIVQ_SHIFT;
+               writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
        }
        writel(reg, hbclk->reg);