ARM: 8453/2: proc-v7.S: don't locate temporary stack space in .text section

The proc-v7.S code uses a small temporary stack to preserve register
content in its setup code. This stack is located in the .text section
which is normally meant to be read-only.

Move that temporary stack to the .bss section and get its address in
a position independent way, similarly to what we do in other parts
of the kernel.

While at it, one comments was updated to reflect reality, and the list
of saved registers in the proc-v7.S case is updated to match the comment
next to it for coherency.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index de2b246fed3808fce444b560a725ed4007464174..2d0ac32320e180595b879da41226a148ae4c7529 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -274,10 +274,12 @@ __v7_ca15mp_setup:
 __v7_b15mp_setup:
 __v7_ca17mp_setup:
        mov     r10, #0
-1:     adr     r12, __v7_setup_stack           @ the local stack
-       stmia   r12, {r0-r5, lr}                @ v7_invalidate_l1 touches r0-r6
+1:     adr     r0, __v7_setup_stack_ptr
+       ldr     r12, [r0]
+       add     r12, r12, r0                    @ the local stack
+       stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
        bl      v7_invalidate_l1
-       ldmia   r12, {r0-r5, lr}
+       ldmia   r12, {r1-r6, lr}
 #ifdef CONFIG_SMP
        ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
        ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
@@ -415,10 +417,12 @@ __v7_pj4b_setup:
 #endif /* CONFIG_CPU_PJ4B */
 
 __v7_setup:
-       adr     r12, __v7_setup_stack           @ the local stack
-       stmia   r12, {r0-r5, lr}                @ v7_invalidate_l1 touches r0-r6
+       adr     r0, __v7_setup_stack_ptr
+       ldr     r12, [r0]
+       add     r12, r12, r0                    @ the local stack
+       stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
        bl      v7_invalidate_l1
-       ldmia   r12, {r0-r5, lr}
+       ldmia   r12, {r1-r6, lr}
 
 __v7_setup_cont:
        and     r0, r9, #0xff000000             @ ARM?
@@ -480,11 +484,16 @@ __errata_finish:
        orr     r0, r0, r6                      @ set them
  THUMB(        orr     r0, r0, #1 << 30        )       @ Thumb exceptions
        ret     lr                              @ return to head.S:__ret
+
+       .align  2
+__v7_setup_stack_ptr:
+       .word   __v7_setup_stack - .
 ENDPROC(__v7_setup)
 
+       .bss
        .align  2
 __v7_setup_stack:
-       .space  4 * 7                           @ 12 registers
+       .space  4 * 7                           @ 7 registers
 
        __INITDATA