drm/i915: check pipe power domain when reading its hw state
authorImre Deak <imre.deak@intel.com>
Wed, 5 Mar 2014 14:20:55 +0000 (16:20 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 7 Mar 2014 21:36:53 +0000 (22:36 +0100)
We can read out the pipe HW state only if the required power domain is
on. If not we consider the pipe to be off.

v2:
- no change
v3:
- push down the power domain checks into the specific crtc
  get_pipe_config handlers (Daniel)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Appease checkpatch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c

index 414da19499f9e9cc9751e02da86bdb648e627f5f..66184423ae291666779f9d9f026b41a57fafe058 100644 (file)
@@ -5611,6 +5611,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t tmp;
 
+       if (!intel_display_power_enabled(dev_priv,
+                                        POWER_DOMAIN_PIPE(crtc->pipe)))
+               return false;
+
        pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
        pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
@@ -6981,6 +6985,10 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
        enum intel_display_power_domain pfit_domain;
        uint32_t tmp;
 
+       if (!intel_display_power_enabled(dev_priv,
+                                        POWER_DOMAIN_PIPE(crtc->pipe)))
+               return false;
+
        pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
        pipe_config->shared_dpll = DPLL_ID_PRIVATE;