arm64: dts: r8a7796: Add Cortex-A53 CPU cores

This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of
6 cores (2 x Cortex-A57 + 4 x Cortex-A53).

Based on a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index b951f5ffe9e0faa0d75853c23146e7966f0a4b0c..b32a180009dd10cc5350471b1cece482fb596408 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -55,6 +55,42 @@
                        enable-method = "psci";
                };
 
+               a53_0: cpu@100 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
+                       next-level-cache = <&L2_CA53>;
+                       enable-method = "psci";
+               };
+
+               a53_1: cpu@101 {
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x101>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
+                       next-level-cache = <&L2_CA53>;
+                       enable-method = "psci";
+               };
+
+               a53_2: cpu@102 {
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x102>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
+                       next-level-cache = <&L2_CA53>;
+                       enable-method = "psci";
+               };
+
+               a53_3: cpu@103 {
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x103>;
+                       device_type = "cpu";
+                       power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
+                       next-level-cache = <&L2_CA53>;
+                       enable-method = "psci";
+               };
+
                L2_CA57: cache-controller-0 {
                        compatible = "cache";
                        power-domains = <&sysc R8A7796_PD_CA57_SCU>;
@@ -115,7 +151,7 @@
                              <0x0 0xf1040000 0 0x20000>,
                              <0x0 0xf1060000 0 0x20000>;
                        interrupts = <GIC_PPI 9
-                                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                                       (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
                        clocks = <&cpg CPG_MOD 408>;
                        clock-names = "clk";
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -124,13 +160,13 @@
                timer {
                        compatible = "arm,armv8-timer";
                        interrupts = <GIC_PPI 13
-                                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                       (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
                                     <GIC_PPI 14
-                                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                       (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
                                     <GIC_PPI 11
-                                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                       (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
                                     <GIC_PPI 10
-                                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+                                       (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
                };
 
                wdt0: watchdog@e6020000 {