[SCSI] mpt3sas: Updated the Hardware timing requirements

Hardware timing requirements is updated in order to comply with firmware
requirement.

Signed-off-by: Sreekanth Reddy <Sreekanth.Reddy@lsi.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 673a1b53a23f3386fbfed3547654e625885b3b5d..5dc280c75325ba775f52c6e4269a4b4c6c6310f5 100644 (file)
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -4090,11 +4090,15 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
        writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
             &ioc->chip->HostDiagnostic);
 
-       /* don't access any registers for 50 milliseconds */
-       msleep(50);
+       /*This delay allows the chip PCIe hardware time to finish reset tasks*/
+       if (sleep_flag == CAN_SLEEP)
+               msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
+       else
+               mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
 
-       /* 300 second max wait */
-       for (count = 0; count < 3000000 ; count++) {
+       /* Approximately 300 second max wait */
+       for (count = 0; count < (300000000 /
+               MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
 
                host_diagnostic = readl(&ioc->chip->HostDiagnostic);
 
@@ -4103,11 +4107,13 @@ _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
                if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
                        break;
 
-               /* wait 1 msec */
+               /* Wait to pass the second read delay window */
                if (sleep_flag == CAN_SLEEP)
-                       usleep_range(1000, 1500);
+                       msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
+                                                               / 1000);
                else
-                       mdelay(1);
+                       mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
+                                                               / 1000);
        }
 
        if (host_diagnostic & MPI2_DIAG_HCB_MODE) {