hdmitx: modify some modes parameters in ENCP

PD#167526: hdmitx: modify some modes parameters in ENCP

480p60hz,576p50hz,720p50/60hz,1080i50/60hz

Change-Id: Ia7b05ccbc20a200eb3684c7f4787e1c31a42cfc3
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
index 5f0d7ed2fb9ec51472208f5423033b127aaa291d..e3789810fef302eec306be936b20afc56352c8f0 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
@@ -2166,6 +2166,10 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
                        if (para->cd != COLORDEPTH_48B)
                                return 0;
                break;
+       case HDMI_720x480i60_16x9:
+       case HDMI_720x576i50_16x9:
+               if (para->cs == COLORSPACE_YUV422)
+                       return 0;
        default:
                break;
        }

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
index d81b7ed3ec9007d08ac1c9dfa0298879c0a159cd..8414c9f6bf3fec53b9c66d578b5d2fa6df2a94bc 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
@@ -48,10 +48,10 @@ static const struct reg_s tvregs_720p[] = {
 
        {P_VENC_DVI_SETTING, 0x2029},
        {P_ENCP_VIDEO_MODE, 0x4040},
-       {P_ENCP_VIDEO_MODE_ADV, 0x0019},
+       {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_YFP1_HTIME, 648},
        {P_ENCP_VIDEO_YFP2_HTIME, 3207},
-       {P_ENCP_VIDEO_MAX_PXCNT, 3299},
+       {P_ENCP_VIDEO_MAX_PXCNT, 1649},
        {P_ENCP_VIDEO_HSPULS_BEGIN, 80},
        {P_ENCP_VIDEO_HSPULS_END, 240},
        {P_ENCP_VIDEO_HSPULS_SWITCH, 80},
@@ -59,11 +59,11 @@ static const struct reg_s tvregs_720p[] = {
        {P_ENCP_VIDEO_VSPULS_END, 3248},
        {P_ENCP_VIDEO_VSPULS_BLINE, 4},
        {P_ENCP_VIDEO_VSPULS_ELINE, 8},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 648},
-       {P_ENCP_VIDEO_HAVON_END, 3207},
-       {P_ENCP_VIDEO_VAVON_BLINE, 29},
-       {P_ENCP_VIDEO_VAVON_ELINE, 748},
-       {P_ENCP_VIDEO_HSO_BEGIN, 256},
+       {P_ENCP_VIDEO_HAVON_BEGIN, 260},
+       {P_ENCP_VIDEO_HAVON_END, 1539},
+       {P_ENCP_VIDEO_VAVON_BLINE, 15},
+       {P_ENCP_VIDEO_VAVON_ELINE, 744},
+       {P_ENCP_VIDEO_HSO_BEGIN, 0},
        {P_ENCP_VIDEO_HSO_END, 168},
        {P_ENCP_VIDEO_VSO_BEGIN, 168},
        {P_ENCP_VIDEO_VSO_END, 256},
@@ -79,30 +79,30 @@ static const struct reg_s tvregs_720p_50hz[] = {
        {P_ENCP_VIDEO_EN, 0},
        {P_ENCI_VIDEO_EN, 0},
        {P_VENC_DVI_SETTING, 0x202d},
-       {P_ENCP_VIDEO_MAX_PXCNT, 3959},
+       {P_ENCP_VIDEO_MAX_PXCNT, 1979},
        {P_ENCP_VIDEO_MAX_LNCNT, 749},
        {P_ENCP_VIDEO_HSPULS_BEGIN, 80},
        {P_ENCP_VIDEO_HSPULS_END, 240},
        {P_ENCP_VIDEO_HSPULS_SWITCH, 80},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 648},
-       {P_ENCP_VIDEO_HAVON_END, 3207},
-       {P_ENCP_VIDEO_HSO_BEGIN, 128},
-       {P_ENCP_VIDEO_HSO_END, 208},
+       {P_ENCP_VIDEO_HAVON_BEGIN, 260},
+       {P_ENCP_VIDEO_HAVON_END, 1539},
+       {P_ENCP_VIDEO_HSO_BEGIN, 0},
+       {P_ENCP_VIDEO_HSO_END, 40},
        {P_ENCP_VIDEO_VSPULS_BEGIN, 688},
        {P_ENCP_VIDEO_VSPULS_END, 3248},
        {P_ENCP_VIDEO_VSPULS_BLINE, 4},
        {P_ENCP_VIDEO_VSPULS_ELINE, 8},
-       {P_ENCP_VIDEO_VAVON_BLINE, 29},
-       {P_ENCP_VIDEO_VAVON_ELINE, 748},
-       {P_ENCP_VIDEO_VSO_BEGIN, 128},
-       {P_ENCP_VIDEO_VSO_END, 128},
+       {P_ENCP_VIDEO_VAVON_BLINE, 25},
+       {P_ENCP_VIDEO_VAVON_ELINE, 744},
+       {P_ENCP_VIDEO_VSO_BEGIN, 30},
+       {P_ENCP_VIDEO_VSO_END, 50},
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_YFP1_HTIME, 648},
        {P_ENCP_VIDEO_YFP2_HTIME, 3207},
        {P_VENC_VIDEO_PROG_MODE, 0x100},
        {P_ENCP_VIDEO_MODE, 0x4040},
-       {P_ENCP_VIDEO_MODE_ADV, 0x0019},
+       {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_SYNC_MODE, 0x407},
        {P_ENCP_VIDEO_YC_DLY, 0},
        {P_ENCP_VIDEO_EN, 1},
@@ -147,10 +147,10 @@ static const struct reg_s tvregs_480p[] = {
        {P_ENCP_VIDEO_FILT_CTRL, 0x2052},
        {P_VENC_DVI_SETTING, 0x21},
        {P_ENCP_VIDEO_MODE, 0x4000},
-       {P_ENCP_VIDEO_MODE_ADV, 9},
+       {P_ENCP_VIDEO_MODE_ADV, 8},
        {P_ENCP_VIDEO_YFP1_HTIME, 244},
        {P_ENCP_VIDEO_YFP2_HTIME, 1630},
-       {P_ENCP_VIDEO_MAX_PXCNT, 1715},
+       {P_ENCP_VIDEO_MAX_PXCNT, 857},
        {P_ENCP_VIDEO_MAX_LNCNT, 524},
        {P_ENCP_VIDEO_HSPULS_BEGIN, 0x22},
        {P_ENCP_VIDEO_HSPULS_END, 0xa0},
@@ -159,17 +159,18 @@ static const struct reg_s tvregs_480p[] = {
        {P_ENCP_VIDEO_VSPULS_END, 1589},
        {P_ENCP_VIDEO_VSPULS_BLINE, 0},
        {P_ENCP_VIDEO_VSPULS_ELINE, 5},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 249},
-       {P_ENCP_VIDEO_HAVON_END, 1689},
-       {P_ENCP_VIDEO_VAVON_BLINE, 42},
-       {P_ENCP_VIDEO_VAVON_ELINE, 521},
+       {P_ENCP_VIDEO_HAVON_BEGIN, 122},
+       {P_ENCP_VIDEO_HAVON_END, 841},
+       {P_ENCP_VIDEO_VAVON_BLINE, 36},
+       {P_ENCP_VIDEO_VAVON_ELINE, 515},
        {P_ENCP_VIDEO_SYNC_MODE, 0x07},
        {P_VENC_VIDEO_PROG_MODE, 0x0},
-       {P_ENCP_VIDEO_HSO_BEGIN, 0x3},
-       {P_ENCP_VIDEO_HSO_END, 0x5},
-       {P_ENCP_VIDEO_VSO_BEGIN, 0x3},
-       {P_ENCP_VIDEO_VSO_END, 0x5},
+       {P_ENCP_VIDEO_HSO_BEGIN, 0},
+       {P_ENCP_VIDEO_HSO_END, 62},
+       {P_ENCP_VIDEO_VSO_BEGIN, 30},
+       {P_ENCP_VIDEO_VSO_END, 50},
        {P_ENCP_VIDEO_VSO_BLINE, 0},
+       {P_ENCP_VIDEO_VSO_ELINE, 6},
        {P_ENCP_VIDEO_SY_VAL, 8},
        {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
        {P_ENCP_DACSEL_0, 0x3102},
@@ -221,10 +222,10 @@ static const struct reg_s tvregs_576p[] = {
        {P_ENCP_VIDEO_FILT_CTRL, 0x52},
        {P_VENC_DVI_SETTING, 0x21},
        {P_ENCP_VIDEO_MODE, 0x4000},
-       {P_ENCP_VIDEO_MODE_ADV, 9},
+       {P_ENCP_VIDEO_MODE_ADV, 8},
        {P_ENCP_VIDEO_YFP1_HTIME, 235},
        {P_ENCP_VIDEO_YFP2_HTIME, 1674},
-       {P_ENCP_VIDEO_MAX_PXCNT, 1727},
+       {P_ENCP_VIDEO_MAX_PXCNT, 863},
        {P_ENCP_VIDEO_MAX_LNCNT, 624},
        {P_ENCP_VIDEO_HSPULS_BEGIN, 0},
        {P_ENCP_VIDEO_HSPULS_END, 0x80},
@@ -233,17 +234,18 @@ static const struct reg_s tvregs_576p[] = {
        {P_ENCP_VIDEO_VSPULS_END, 1599},
        {P_ENCP_VIDEO_VSPULS_BLINE, 0},
        {P_ENCP_VIDEO_VSPULS_ELINE, 4},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 235},
-       {P_ENCP_VIDEO_HAVON_END, 1674},
+       {P_ENCP_VIDEO_HAVON_BEGIN, 132},
+       {P_ENCP_VIDEO_HAVON_END, 851},
        {P_ENCP_VIDEO_VAVON_BLINE, 44},
        {P_ENCP_VIDEO_VAVON_ELINE, 619},
        {P_ENCP_VIDEO_SYNC_MODE, 0x07},
        {P_VENC_VIDEO_PROG_MODE, 0x0},
-       {P_ENCP_VIDEO_HSO_BEGIN, 0x80},
-       {P_ENCP_VIDEO_HSO_END, 0x0},
-       {P_ENCP_VIDEO_VSO_BEGIN, 0x0},
-       {P_ENCP_VIDEO_VSO_END, 0x5},
+       {P_ENCP_VIDEO_HSO_BEGIN, 0},
+       {P_ENCP_VIDEO_HSO_END, 64},
+       {P_ENCP_VIDEO_VSO_BEGIN, 30},
+       {P_ENCP_VIDEO_VSO_END, 50},
        {P_ENCP_VIDEO_VSO_BLINE, 0},
+       {P_ENCP_VIDEO_VSO_BLINE, 5},
        {P_ENCP_VIDEO_SY_VAL, 8},
        {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
        {P_ENCI_VIDEO_EN, 0},
@@ -255,15 +257,15 @@ static const struct reg_s tvregs_1080i[] = {
        {P_ENCP_VIDEO_EN, 0},
        {P_ENCI_VIDEO_EN, 0},
        {P_VENC_DVI_SETTING, 0x2029},
-       {P_ENCP_VIDEO_MAX_PXCNT, 4399},
+       {P_ENCP_VIDEO_MAX_PXCNT, 2199},
        {P_ENCP_VIDEO_MAX_LNCNT, 1124},
        {P_ENCP_VIDEO_HSPULS_BEGIN, 88},
        {P_ENCP_VIDEO_HSPULS_END, 264},
        {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 516},
-       {P_ENCP_VIDEO_HAVON_END, 4355},
-       {P_ENCP_VIDEO_HSO_BEGIN, 264},
-       {P_ENCP_VIDEO_HSO_END, 176},
+       {P_ENCP_VIDEO_HAVON_BEGIN, 192},
+       {P_ENCP_VIDEO_HAVON_END, 2111},
+       {P_ENCP_VIDEO_HSO_BEGIN, 0},
+       {P_ENCP_VIDEO_HSO_END, 44},
        {P_ENCP_VIDEO_EQPULS_BEGIN, 2288},
        {P_ENCP_VIDEO_EQPULS_END, 2464},
        {P_ENCP_VIDEO_VSPULS_BEGIN, 440},
@@ -274,8 +276,8 @@ static const struct reg_s tvregs_1080i[] = {
        {P_ENCP_VIDEO_EQPULS_ELINE, 4},
        {P_ENCP_VIDEO_VAVON_BLINE, 20},
        {P_ENCP_VIDEO_VAVON_ELINE, 559},
-       {P_ENCP_VIDEO_VSO_BEGIN, 88},
-       {P_ENCP_VIDEO_VSO_END, 88},
+       {P_ENCP_VIDEO_VSO_BEGIN, 30},
+       {P_ENCP_VIDEO_VSO_END, 50},
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_YFP1_HTIME, 516},
@@ -283,7 +285,7 @@ static const struct reg_s tvregs_1080i[] = {
        {P_VENC_VIDEO_PROG_MODE, 0x100},
        {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11},
        {P_ENCP_VIDEO_MODE, 0x5ffc},
-       {P_ENCP_VIDEO_MODE_ADV, 0x0019},
+       {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_SYNC_MODE, 0x207},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
@@ -294,23 +296,23 @@ static const struct reg_s tvregs_1080i_50hz[] = {
        {P_ENCP_VIDEO_EN, 0},
        {P_ENCI_VIDEO_EN, 0},
        {P_VENC_DVI_SETTING, 0x202d},
-       {P_ENCP_VIDEO_MAX_PXCNT, 5279},
+       {P_ENCP_VIDEO_MAX_PXCNT, 2639},
        {P_ENCP_VIDEO_MAX_LNCNT, 1124},
        {P_ENCP_VIDEO_HSPULS_BEGIN, 88},
        {P_ENCP_VIDEO_HSPULS_END, 264},
        {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 526},
-       {P_ENCP_VIDEO_HAVON_END, 4365},
-       {P_ENCP_VIDEO_HSO_BEGIN, 142},
-       {P_ENCP_VIDEO_HSO_END, 230},
+       {P_ENCP_VIDEO_HAVON_BEGIN, 192},
+       {P_ENCP_VIDEO_HAVON_END, 2111},
+       {P_ENCP_VIDEO_HSO_BEGIN, 0},
+       {P_ENCP_VIDEO_HSO_END, 44},
        {P_ENCP_VIDEO_VSPULS_BEGIN, 440},
        {P_ENCP_VIDEO_VSPULS_END, 2200},
        {P_ENCP_VIDEO_VSPULS_BLINE, 0},
        {P_ENCP_VIDEO_VSPULS_ELINE, 4},
        {P_ENCP_VIDEO_VAVON_BLINE, 20},
        {P_ENCP_VIDEO_VAVON_ELINE, 559},
-       {P_ENCP_VIDEO_VSO_BEGIN, 142},
-       {P_ENCP_VIDEO_VSO_END, 142},
+       {P_ENCP_VIDEO_VSO_BEGIN, 30},
+       {P_ENCP_VIDEO_VSO_END, 50},
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_YFP1_HTIME, 526},
@@ -318,7 +320,7 @@ static const struct reg_s tvregs_1080i_50hz[] = {
        {P_VENC_VIDEO_PROG_MODE, 0x100},
        {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11},
        {P_ENCP_VIDEO_MODE, 0x5ffc},
-       {P_ENCP_VIDEO_MODE_ADV, 0x0019},
+       {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_SYNC_MODE, 0x7},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index f41599450acbe5768db11203d27b332995bfccb8..5bedbecca977560692288bcd4591b341033e7720 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -732,7 +732,7 @@ static void hdmi_tvenc1080i_set(struct hdmitx_vidpara *param)
 
        if (param->VIC == HDMI_1080i60) {
                INTERLACE_MODE = 1;
-               PIXEL_REPEAT_VENC = 1;
+               PIXEL_REPEAT_VENC = 0;
                PIXEL_REPEAT_HDMI = 0;
                ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
                ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
@@ -747,7 +747,7 @@ static void hdmi_tvenc1080i_set(struct hdmitx_vidpara *param)
                TOTAL_FRAMES = 4;
        } else if (param->VIC == HDMI_1080i50) {
                INTERLACE_MODE = 1;
-               PIXEL_REPEAT_VENC = 1;
+               PIXEL_REPEAT_VENC = 0;
                PIXEL_REPEAT_HDMI = 0;
                ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
                ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
@@ -840,7 +840,7 @@ static void hdmi_tvenc1080i_set(struct hdmitx_vidpara *param)
                (VSYNC_POLARITY << 3) |
                (0 << 4) |
                (4 << 5) |
-               (1 << 8) |
+               (0 << 8) |
                (0 << 12)
        );
        hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
@@ -1314,7 +1314,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
        case HDMI_480p60_16x9:
        case HDMI_480p60_16x9_rpt:
                INTERLACE_MODE = 0U;
-               PIXEL_REPEAT_VENC = 1;
+               PIXEL_REPEAT_VENC = 0;
                PIXEL_REPEAT_HDMI = 0;
                ACTIVE_PIXELS   = (720*(1+PIXEL_REPEAT_HDMI));
                ACTIVE_LINES = (480/(1+INTERLACE_MODE));
@@ -1332,7 +1332,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
        case HDMI_576p50_16x9:
        case HDMI_576p50_16x9_rpt:
                INTERLACE_MODE = 0U;
-               PIXEL_REPEAT_VENC = 1;
+               PIXEL_REPEAT_VENC = 0;
                PIXEL_REPEAT_HDMI = 0;
                ACTIVE_PIXELS   = (720*(1+PIXEL_REPEAT_HDMI));
                ACTIVE_LINES = (576/(1+INTERLACE_MODE));
@@ -1348,7 +1348,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
                break;
        case HDMI_720p60:
                INTERLACE_MODE = 0U;
-               PIXEL_REPEAT_VENC = 1;
+               PIXEL_REPEAT_VENC = 0;
                PIXEL_REPEAT_HDMI = 0;
                ACTIVE_PIXELS   = (1280*(1+PIXEL_REPEAT_HDMI));
                ACTIVE_LINES = (720/(1+INTERLACE_MODE));
@@ -1364,7 +1364,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
                break;
        case HDMI_720p50:
                INTERLACE_MODE = 0U;
-               PIXEL_REPEAT_VENC = 1;
+               PIXEL_REPEAT_VENC = 0;
                PIXEL_REPEAT_HDMI = 0;
                ACTIVE_PIXELS   = (1280*(1+PIXEL_REPEAT_HDMI));
                ACTIVE_LINES = (720/(1+INTERLACE_MODE));
@@ -1521,7 +1521,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
                                (VSYNC_POLARITY << 3) |
                                (0 << 4) |
                                (0 << 5) |
-                               (1 << 8) |
+                               (0 << 8) |
                                (0 << 12)
                );
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
@@ -1564,7 +1564,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
                                (0 << 3) |
                                (0 << 4) |
                                (4 << 5) |
-                               (1 << 8) |
+                               (0 << 8) |
                                (0 << 12)
                );
                if ((param->VIC == HDMI_480p60_16x9_rpt) ||
@@ -1580,7 +1580,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
                                (VSYNC_POLARITY << 3) |
                                (0 << 4) |
                                (4 << 5) |
-                               (1 << 8) |
+                               (0 << 8) |
                                (0 << 12)
                );
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
@@ -1886,7 +1886,6 @@ void hdmitx_set_enc_hw(struct hdmitx_dev *hdev)
        if (hdev->para->cs == COLORSPACE_YUV422) {
                hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 1, 0, 2);
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4);
-               hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1);
        }
 
        switch (hdev->para->cd) {

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
index 445ce55e1b94e798dfa723ee5a8fc2d2f9185598..29218aa716f130f580f843601f123a28746128cc 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -733,15 +733,15 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
        {{HDMI_720x576p50_16x9,
          HDMI_720x480p60_16x9,
          HDMI_VIC_END},
-               4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+               4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
        {{HDMI_1280x720p50_16x9,
          HDMI_1280x720p60_16x9,
          HDMI_VIC_END},
-               5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+               5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
        {{HDMI_1920x1080i60_16x9,
          HDMI_1920x1080i50_16x9,
          HDMI_VIC_END},
-               5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+               5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
        {{HDMI_1920x1080p60_16x9,
          HDMI_1920x1080p50_16x9,
          HDMI_VIC_END},
@@ -785,15 +785,15 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
        {{HDMI_720x576p50_16x9,
          HDMI_720x480p60_16x9,
          HDMI_VIC_END},
-               5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
+               5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
        {{HDMI_1280x720p50_16x9,
          HDMI_1280x720p60_16x9,
          HDMI_VIC_END},
-               3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
+               3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
        {{HDMI_1920x1080i60_16x9,
          HDMI_1920x1080i50_16x9,
          HDMI_VIC_END},
-               3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
+               3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
        {{HDMI_1920x1080p60_16x9,
          HDMI_1920x1080p50_16x9,
          HDMI_VIC_END},
@@ -831,15 +831,15 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
        {{HDMI_720x576p50_16x9,
          HDMI_720x480p60_16x9,
          HDMI_VIC_END},
-               3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
+               3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
        {{HDMI_1280x720p50_16x9,
          HDMI_1280x720p60_16x9,
          HDMI_VIC_END},
-               4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
+               4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
        {{HDMI_1920x1080i60_16x9,
          HDMI_1920x1080i50_16x9,
          HDMI_VIC_END},
-               4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
+               4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
        {{HDMI_1920x1080p60_16x9,
          HDMI_1920x1080p50_16x9,
          HDMI_VIC_END},