osd: add osd blend reg config check. [1/4]

PD#SWPL-2049

Problem:
osd3 din blend config may be incorrect when viu2 is enable

Solution:
add osd blend reg config check

Verify:
verify by AC202(sm1)

Change-Id: I3d8ff0d247226d4df1386808caba2a21a34f0b10
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>

diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c
index dbe8ffe0feb0ed54ecc5eb3ece656f8c6301c2d0..ad095b86118310e3947731aa0d43c18073df06e2 100644 (file)
--- a/drivers/amlogic/media/osd/osd_hw.c
+++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -8363,18 +8363,13 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg)
                VSYNCOSD_WR_MPEG_REG(
                        VIU_OSD_BLEND_DIN0_SCOPE_H + reg_offset * i,
                        blend_reg->osd_blend_din_scope_h[i]);
+               }
+               if ((blend_reg->osd_blend_din_scope_v[i] & 0xffff0000) == 0)
+                       blend_reg->osd_blend_din_scope_v[i] =
+                               0xffffffff;
                VSYNCOSD_WR_MPEG_REG(
                        VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i,
                        blend_reg->osd_blend_din_scope_v[i]);
-               }
-               else {
-                       if ((blend_reg->osd_blend_din_scope_v[i] & 0xffff) == 0)
-                               blend_reg->osd_blend_din_scope_v[i] =
-                                       0xffffffff;
-                       VSYNCOSD_WR_MPEG_REG(
-                               VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i,
-                               blend_reg->osd_blend_din_scope_v[i]);
-               }
        }
 
        dv_core2_vsize = (blend_reg->osd_blend_blend0_size >> 16) & 0xfff;