void xlp_mmu_init(void);
void nlm_hal_init(void);
-int xlp_get_dram_map(int n, uint64_t *dram_map);
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
struct pci_dev;
int xlp_socdev_to_node(const struct pci_dev *dev);
/*
* Fills upto 8 pairs of entries containing the DRAM map of a node
- * if n < 0, get dram map for all nodes
+ * if node < 0, get dram map for all nodes
*/
-int xlp_get_dram_map(int n, uint64_t *dram_map)
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries)
{
uint64_t bridgebase, base, lim;
uint32_t val;
unsigned int barreg, limreg, xlatreg;
- int i, node, rv;
+ int i, n, rv;
/* Look only at mapping on Node 0, we don't handle crazy configs */
bridgebase = nlm_get_bridge_regbase(0);
rv = 0;
for (i = 0; i < 8; i++) {
+ if (rv + 1 >= nentries)
+ break;
if (cpu_is_xlp9xx()) {
barreg = BRIDGE_9XX_DRAM_BAR(i);
limreg = BRIDGE_9XX_DRAM_LIMIT(i);
limreg = BRIDGE_DRAM_LIMIT(i);
xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
}
- if (n >= 0) {
+ if (node >= 0) {
/* node specified, get node mapping of BAR */
val = nlm_read_bridge_reg(bridgebase, xlatreg);
- node = (val >> 1) & 0x3;
+ n = (val >> 1) & 0x3;
if (n != node)
continue;
}
uint64_t map[16];
int i, n;
- n = xlp_get_dram_map(-1, map); /* -1: info for all nodes */
+ n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map)); /* -1 : all nodes */
for (i = 0; i < n; i += 2) {
/* exclude 0x1000_0000-0x2000_0000, u-boot device */
if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)