clk/exynos5250: add sclk_hdmiphy in the list of special clocks

hdmi driver needs hdmiphy clock which is one of the parent
for hdmi mux clock. This is required while changing the parent
of mux clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 76b97c92870cdbbba4955661e6c35e290c19ed03..24765c146e31d52ea4c732812c420ccdb5d3e670 100644 (file)
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -61,6 +61,7 @@ clock which they consume.
   sclk_spi2            156
   div_i2s1             157
   div_i2s2             158
+  sclk_hdmiphy         159
 
 
    [Peripheral Clock Gates]

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 397f1ca41b9700070dd863d0b84b5effb86088a8..4361f4a0bdb372a9bffdfad96ec5aeff4b5ea0f0 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -88,7 +88,7 @@ enum exynos5250_clks {
        sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
        sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
        sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
-       div_i2s1, div_i2s2,
+       div_i2s1, div_i2s2, sclk_hdmiphy,
 
        /* gate clocks */
        gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -202,7 +202,7 @@ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initda
 
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
-       FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+       FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
        FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
        FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
        FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),