drm/amdgpu: enable BUS master after pci reset
authorChunming Zhou <David1.Zhou@amd.com>
Mon, 6 Jun 2016 05:50:18 +0000 (13:50 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 7 Jul 2016 18:51:25 +0000 (14:51 -0400)
Re-enable bus mastering after GPU reset. We disable it
at the top of these functions, so balance them by
re-enabling it.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
eviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/vi.c

index 4c21c881ef41ae87af49423effbc2d791b335a6e..4c80338992adce8805fd0dd614021072ea96b685 100644 (file)
@@ -1179,6 +1179,8 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
                if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
+                       /* enable BM */
+                       pci_set_master(adev->pdev);
                        r = 0;
                        break;
                }
index 064122bfa6f95903bc89da6aeb8cd01be5b2414c..e05e722ef6c713ecbfd523097bc1adb7b5debaa9 100644 (file)
@@ -612,8 +612,11 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
-               if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
+               if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
+                       /* enable BM */
+                       pci_set_master(adev->pdev);
                        return 0;
+               }
                udelay(1);
        }
        return -EINVAL;