ASoC: clean up wm8974 and wm8978 clock divider handling
authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Fri, 29 Jan 2010 14:31:06 +0000 (15:31 +0100)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Fri, 29 Jan 2010 14:32:52 +0000 (14:32 +0000)
wm8974 and wm8978 codec drivers control DAC and ADC oversampling rates in their
.set_clkdiv() methods, which is wrong, because these are simple boolean
switches and not clock dividers. Move these bits to sound controls. Also remove
manual configuration of the MCLK divider in wm8978, since it is configured
automatically.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
sound/soc/codecs/wm8974.c
sound/soc/codecs/wm8974.h
sound/soc/codecs/wm8978.c
sound/soc/codecs/wm8978.h
sound/soc/sh/migor.c

index 8812751da8c9838c484ffe66ae1d0e0eb8858546..ee637af4737a039c252c82c287f5c37e22b4ee37 100644 (file)
@@ -170,6 +170,10 @@ SOC_ENUM("Aux Mode", wm8974_auxmode),
 
 SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST,  8, 1, 0),
 SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 1),
+
+/* DAC / ADC oversampling */
+SOC_SINGLE("DAC 128x Oversampling Switch", WM8974_DAC, 8, 1, 0),
+SOC_SINGLE("ADC 128x Oversampling Switch", WM8974_ADC, 8, 1, 0),
 };
 
 /* Speaker Output Mixer */
@@ -381,14 +385,6 @@ static int wm8974_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
                reg = snd_soc_read(codec, WM8974_CLOCK) & 0x11f;
                snd_soc_write(codec, WM8974_CLOCK, reg | div);
                break;
-       case WM8974_ADCCLK:
-               reg = snd_soc_read(codec, WM8974_ADC) & 0x1f7;
-               snd_soc_write(codec, WM8974_ADC, reg | div);
-               break;
-       case WM8974_DACCLK:
-               reg = snd_soc_read(codec, WM8974_DAC) & 0x1f7;
-               snd_soc_write(codec, WM8974_DAC, reg | div);
-               break;
        case WM8974_BCLKDIV:
                reg = snd_soc_read(codec, WM8974_CLOCK) & 0x1e3;
                snd_soc_write(codec, WM8974_CLOCK, reg | div);
index 98de9562d4d240bae85d158563f6279d45819ae7..896a7f0f3fc4b189e0537bb6f7765639e2957b65 100644 (file)
 /* Clock divider Id's */
 #define WM8974_OPCLKDIV                0
 #define WM8974_MCLKDIV         1
-#define WM8974_ADCCLK          2
-#define WM8974_DACCLK          3
-#define WM8974_BCLKDIV         4
-
-/* DAC clock dividers */
-#define WM8974_DACCLK_F2       (1 << 3)
-#define WM8974_DACCLK_F4       (0 << 3)
-
-/* ADC clock dividers */
-#define WM8974_ADCCLK_F2       (1 << 3)
-#define WM8974_ADCCLK_F4       (0 << 3)
+#define WM8974_BCLKDIV         2
 
 /* PLL Out dividers */
 #define WM8974_OPCLKDIV_1      (0 << 4)
index 8dcebaa8604a32c4018c9c0084bbc35b4fb86f83..ec2624b4c37072b3002f0b8f43d1a5b2a804336f 100644 (file)
@@ -210,6 +210,10 @@ static const struct snd_kcontrol_new wm8978_snd_controls[] = {
        /* Speaker */
        SOC_DOUBLE_R("Speaker Switch",
                WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
+
+       /* DAC / ADC oversampling */
+       SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0),
+       SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0),
 };
 
 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
@@ -513,21 +517,6 @@ static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
                if (wm8978->f_mclk)
                        ret = wm8978_configure_pll(codec);
                break;
-       case WM8978_MCLKDIV:
-               if (div & ~0xe0)
-                       return -EINVAL;
-               snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, div);
-               break;
-       case WM8978_ADCCLK:
-               if (div & ~8)
-                       return -EINVAL;
-               snd_soc_update_bits(codec, WM8978_ADC_CONTROL, 8, div);
-               break;
-       case WM8978_DACCLK:
-               if (div & ~8)
-                       return -EINVAL;
-               snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 8, div);
-               break;
        case WM8978_BCLKDIV:
                if (div & ~0x1c)
                        return -EINVAL;
index b58f0bf947e76c3631b21e9aef1a4bf0930fbc29..56ec83270917db070872ea5a9756e83b9bf16220 100644 (file)
@@ -72,9 +72,6 @@
 /* Clock divider Id's */
 enum wm8978_clk_id {
        WM8978_OPCLKRATE,
-       WM8978_MCLKDIV,
-       WM8978_ADCCLK,
-       WM8978_DACCLK,
        WM8978_BCLKDIV,
 };
 
index 3ccd9b393312a9b4b8c6bc273135fca37a0818f6..b823a5c9b9bc81d81b8f64f4847483eae3f253bc 100644 (file)
@@ -59,10 +59,6 @@ static int migor_hw_params(struct snd_pcm_substream *substream,
        if (ret < 0)
                return ret;
 
-       ret = snd_soc_dai_set_clkdiv(codec_dai, WM8978_DACCLK, 8);
-       if (ret < 0)
-               return ret;
-
        ret = snd_soc_dai_set_clkdiv(codec_dai, WM8978_OPCLKRATE, rate * 512);
        if (ret < 0)
                return ret;