SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST, 8, 1, 0),
SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 1),
+
+/* DAC / ADC oversampling */
+SOC_SINGLE("DAC 128x Oversampling Switch", WM8974_DAC, 8, 1, 0),
+SOC_SINGLE("ADC 128x Oversampling Switch", WM8974_ADC, 8, 1, 0),
};
/* Speaker Output Mixer */
reg = snd_soc_read(codec, WM8974_CLOCK) & 0x11f;
snd_soc_write(codec, WM8974_CLOCK, reg | div);
break;
- case WM8974_ADCCLK:
- reg = snd_soc_read(codec, WM8974_ADC) & 0x1f7;
- snd_soc_write(codec, WM8974_ADC, reg | div);
- break;
- case WM8974_DACCLK:
- reg = snd_soc_read(codec, WM8974_DAC) & 0x1f7;
- snd_soc_write(codec, WM8974_DAC, reg | div);
- break;
case WM8974_BCLKDIV:
reg = snd_soc_read(codec, WM8974_CLOCK) & 0x1e3;
snd_soc_write(codec, WM8974_CLOCK, reg | div);
/* Clock divider Id's */
#define WM8974_OPCLKDIV 0
#define WM8974_MCLKDIV 1
-#define WM8974_ADCCLK 2
-#define WM8974_DACCLK 3
-#define WM8974_BCLKDIV 4
-
-/* DAC clock dividers */
-#define WM8974_DACCLK_F2 (1 << 3)
-#define WM8974_DACCLK_F4 (0 << 3)
-
-/* ADC clock dividers */
-#define WM8974_ADCCLK_F2 (1 << 3)
-#define WM8974_ADCCLK_F4 (0 << 3)
+#define WM8974_BCLKDIV 2
/* PLL Out dividers */
#define WM8974_OPCLKDIV_1 (0 << 4)
/* Speaker */
SOC_DOUBLE_R("Speaker Switch",
WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
+
+ /* DAC / ADC oversampling */
+ SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0),
+ SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0),
};
/* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
if (wm8978->f_mclk)
ret = wm8978_configure_pll(codec);
break;
- case WM8978_MCLKDIV:
- if (div & ~0xe0)
- return -EINVAL;
- snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, div);
- break;
- case WM8978_ADCCLK:
- if (div & ~8)
- return -EINVAL;
- snd_soc_update_bits(codec, WM8978_ADC_CONTROL, 8, div);
- break;
- case WM8978_DACCLK:
- if (div & ~8)
- return -EINVAL;
- snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 8, div);
- break;
case WM8978_BCLKDIV:
if (div & ~0x1c)
return -EINVAL;
/* Clock divider Id's */
enum wm8978_clk_id {
WM8978_OPCLKRATE,
- WM8978_MCLKDIV,
- WM8978_ADCCLK,
- WM8978_DACCLK,
WM8978_BCLKDIV,
};
if (ret < 0)
return ret;
- ret = snd_soc_dai_set_clkdiv(codec_dai, WM8978_DACCLK, 8);
- if (ret < 0)
- return ret;
-
ret = snd_soc_dai_set_clkdiv(codec_dai, WM8978_OPCLKRATE, rate * 512);
if (ret < 0)
return ret;