Merge branches 'devel-iommu-mailbox', 'devel-mcbsp', 'devel-board' and 'devel-hsmmc...

Conflicts:
	arch/arm/mach-omap2/omap_hwmod_44xx_data.c

diff --cc arch/arm/mach-omap2/board-2430sdp.c
Simple merge

diff --cc arch/arm/mach-omap2/board-3430sdp.c
Simple merge

diff --cc arch/arm/mach-omap2/board-4430sdp.c
Simple merge

diff --cc arch/arm/mach-omap2/board-devkit8000.c
Simple merge

diff --cc arch/arm/mach-omap2/board-igep0020.c
Simple merge

diff --cc arch/arm/mach-omap2/board-omap3evm.c
index 7341f966bf1a5e8be1cfdcc90b229d9918166163,5364147892c1dc361d8a6862f52718809179f0ba,5364147892c1dc361d8a6862f52718809179f0ba,a8b1fefc63db0fd5c3fee8a89fbd6a4a236c1bb8,f2a3a883cca5fc036b2f84e342190d17dafcdb29..b65848c59e1d3ab2340d985bcd2aa0ea338d6119
--- 1/arch/arm/mach-omap2/board-omap3evm.c
--- 2/arch/arm/mach-omap2/board-omap3evm.c
--- 3/arch/arm/mach-omap2/board-omap3evm.c
--- 4/arch/arm/mach-omap2/board-omap3evm.c
--- 5/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@@@@@ -603,8 -603,10 -603,10 -601,10 -603,8 +601,8 @@@@@@ static struct regulator_init_data omap3
     #define OMAP3EVM_WLAN_PMENA_GPIO   (150)
     #define OMAP3EVM_WLAN_IRQ_GPIO             (149)
     
 --- static struct regulator_consumer_supply omap3evm_vmmc2_supply = {
 ---    .supply                 = "vmmc",
 ---    .dev_name               = "mmci-omap-hs.1",
 --- };
 +++ static struct regulator_consumer_supply omap3evm_vmmc2_supply =
-       REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
++++    REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
     
     /* VMMC2 for driving the WL12xx module */
     static struct regulator_init_data omap3evm_vmmc2 = {

diff --cc arch/arm/mach-omap2/board-omap3pandora.c
Simple merge

diff --cc arch/arm/mach-omap2/board-omap4panda.c
Simple merge

diff --cc arch/arm/mach-omap2/board-rx51-peripherals.c
Simple merge

diff --cc arch/arm/mach-omap2/board-zoom-peripherals.c
Simple merge

diff --cc arch/arm/mach-omap2/devices.c
index 9ee876fd367ad3f54040f506b54c96d3fe7aed16,d216976988d759b1facffac8f27542e9956f0edf,d216976988d759b1facffac8f27542e9956f0edf,9ee876fd367ad3f54040f506b54c96d3fe7aed16,31632ac1ca7c19d27dbcc470e714db0cbd0ce28f..2cb720b5b12ede09dc16b7bf39e36ff127c87e68
--- 1/arch/arm/mach-omap2/devices.c
--- 2/arch/arm/mach-omap2/devices.c
--- 3/arch/arm/mach-omap2/devices.c
--- 4/arch/arm/mach-omap2/devices.c
--- 5/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@@@@@ -544,117 -478,117 -478,117 -544,117 -544,10 +478,10 @@@@@@ static inline void omap_init_aes(void) 
     
     /*-------------------------------------------------------------------------*/
     
---- #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-  - 
-  - #define MMCHS_SYSCONFIG                    0x0010
-  - #define MMCHS_SYSCONFIG_SWRESET            (1 << 1)
-  - #define MMCHS_SYSSTATUS                    0x0014
-  - #define MMCHS_SYSSTATUS_RESETDONE  (1 << 0)
++++ #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
     
 --  #define MMCHS_SYSCONFIG                    0x0010
 --  #define MMCHS_SYSCONFIG_SWRESET            (1 << 1)
 --  #define MMCHS_SYSSTATUS                    0x0014
 --  #define MMCHS_SYSSTATUS_RESETDONE  (1 << 0)
 --  
---- static struct platform_device dummy_pdev = {
----    .dev = {
----            .bus = &platform_bus_type,
----    },
---- };
---- 
---- /**
----  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
----  *
----  * Ensure that each MMC controller is fully reset.  Controllers
----  * left in an unknown state (by bootloader) may prevent retention
----  * or OFF-mode.  This is especially important in cases where the
----  * MMC driver is not enabled, _or_ built as a module.
----  *
----  * In order for reset to work, interface, functional and debounce
----  * clocks must be enabled.  The debounce clock comes from func_32k_clk
----  * and is not under SW control, so we only enable i- and f-clocks.
----  **/
---- static void __init omap_hsmmc_reset(void)
---- {
----    u32 i, nr_controllers;
----    struct clk *iclk, *fclk;
---- 
----    if (cpu_is_omap242x())
----            return;
---- 
----    nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
----            (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
---- 
----    for (i = 0; i < nr_controllers; i++) {
----            u32 v, base = 0;
----            struct device *dev = &dummy_pdev.dev;
---- 
----            switch (i) {
----            case 0:
----                    base = OMAP2_MMC1_BASE;
----                    break;
----            case 1:
----                    base = OMAP2_MMC2_BASE;
----                    break;
----            case 2:
----                    base = OMAP3_MMC3_BASE;
----                    break;
----            case 3:
----                    if (!cpu_is_omap44xx())
----                            return;
----                    base = OMAP4_MMC4_BASE;
----                    break;
----            case 4:
----                    if (!cpu_is_omap44xx())
----                            return;
----                    base = OMAP4_MMC5_BASE;
----                    break;
----            }
---- 
----            if (cpu_is_omap44xx())
----                    base += OMAP4_MMC_REG_OFFSET;
---- 
----            dummy_pdev.id = i;
----            dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
----            iclk = clk_get(dev, "ick");
----            if (IS_ERR(iclk))
----                    goto err1;
----            if (clk_enable(iclk))
----                    goto err2;
---- 
----            fclk = clk_get(dev, "fck");
----            if (IS_ERR(fclk))
----                    goto err3;
----            if (clk_enable(fclk))
----                    goto err4;
---- 
----            omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
----            v = omap_readl(base + MMCHS_SYSSTATUS);
----            while (!(omap_readl(base + MMCHS_SYSSTATUS) &
----                     MMCHS_SYSSTATUS_RESETDONE))
----                    cpu_relax();
---- 
----            clk_disable(fclk);
----            clk_put(fclk);
----            clk_disable(iclk);
----            clk_put(iclk);
----    }
----    return;
---- 
---- err4:
----    clk_put(fclk);
---- err3:
----    clk_disable(iclk);
---- err2:
----    clk_put(iclk);
---- err1:
----    printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
----                        "cannot reset.\n",  __func__, i);
---- }
---- #else
---- static inline void omap_hsmmc_reset(void) {}
---- #endif
---- 
---- #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
----    defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
---- 
---- static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
----                    int controller_nr)
++++ static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
++++                                                    *mmc_controller)
     {
        if ((mmc_controller->slots[0].switch_pin > 0) && \
                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))

diff --cc arch/arm/mach-omap2/mailbox.c
Simple merge

diff --cc arch/arm/mach-omap2/omap_hwmod.c
Simple merge

diff --cc arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e58621aa9b34eaa4df2e204b7a44c0903ab19c7e,19ad9d053dede72d5b47ee66fb56fdeb0847f443,e44ecb465519b6eb78f8d716d34185f0a05c76c3,f323c6bb22de8191d788e519c09b27353fc5676d,e58621aa9b34eaa4df2e204b7a44c0903ab19c7e..e0bc2c7a15de69eb65a4979a0baaab9941d3c8fc
--- 1/arch/arm/mach-omap2/omap_hwmod_2420_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_2420_data.c
--- 3/arch/arm/mach-omap2/omap_hwmod_2420_data.c
--- 4/arch/arm/mach-omap2/omap_hwmod_2420_data.c
--- 5/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@@@@@ -1982,6 -1418,9 -1543,13 -1348,6 -1982,6 +2177,13 @@@@@@ static __initdata struct omap_hwmod *om
        /* dma_system class*/
        &omap2420_dma_system_hwmod,
     
+  ++   /* mailbox class */
+  ++   &omap2420_mailbox_hwmod,
+  ++
++ ++   /* mcbsp class */
++ ++   &omap2420_mcbsp1_hwmod,
++ ++   &omap2420_mcbsp2_hwmod,
++ ++
        /* mcspi class */
        &omap2420_mcspi1_hwmod,
        &omap2420_mcspi2_hwmod,

diff --cc arch/arm/mach-omap2/omap_hwmod_2430_data.c
index b46a54ce1a41fe91bbfd0543815062382c5dd297,91d2581c770a1fb96930e32bd1b307f6fd0d4623,1e65a4f5117bdd315b69d66754d0a0dc0760add2,de0015d38433de9d34808a929ca108aea31fc868,ca25fa2af78f982d5f06b22b5e786b60902600ca..4aa74d78289ccd3ff72928ad826a12d63b808e56
--- 1/arch/arm/mach-omap2/omap_hwmod_2430_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_2430_data.c
--- 3/arch/arm/mach-omap2/omap_hwmod_2430_data.c
--- 4/arch/arm/mach-omap2/omap_hwmod_2430_data.c
--- 5/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@@@@@ -18,8 -18,7 -18,8 -18,7 -18,9 +18,10 @@@@@@
     #include <plat/serial.h>
     #include <plat/i2c.h>
     #include <plat/gpio.h>
++ ++#include <plat/mcbsp.h>
     #include <plat/mcspi.h>
 +++ #include <plat/dmtimer.h>
++++ #include <plat/mmc.h>
     #include <plat/l3_2xxx.h>
     
     #include "omap_hwmod_common_data.h"
@@@@@@ -356,662 -355,44 -361,44 -355,44 -397,662 +403,662 @@@@@@ static struct omap_hwmod_ocp_if *omap24
        &omap2430_mpu__l3_main,
     };
     
   - /* MPU */
   - static struct omap_hwmod omap2430_mpu_hwmod = {
   -    .name           = "mpu",
   -    .class          = &mpu_hwmod_class,
   -    .main_clk       = "mpu_ck",
   -    .masters        = omap2430_mpu_masters,
   -    .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
   -    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
   + /* MPU */
   + static struct omap_hwmod omap2430_mpu_hwmod = {
   +    .name           = "mpu",
   +    .class          = &mpu_hwmod_class,
   +    .main_clk       = "mpu_ck",
   +    .masters        = omap2430_mpu_masters,
   +    .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
   +    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
   + };
   + 
   + /*
   +  * IVA2_1 interface data
   +  */
   + 
   + /* IVA2 <- L3 interface */
   + static struct omap_hwmod_ocp_if omap2430_l3__iva = {
   +    .master         = &omap2430_l3_main_hwmod,
   +    .slave          = &omap2430_iva_hwmod,
   +    .clk            = "dsp_fck",
   +    .user           = OCP_USER_MPU | OCP_USER_SDMA,
   + };
   + 
   + static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
   +    &omap2430_l3__iva,
   + };
   + 
   + /*
   +  * IVA2 (IVA2)
   +  */
   + 
   + static struct omap_hwmod omap2430_iva_hwmod = {
   +    .name           = "iva",
   +    .class          = &iva_hwmod_class,
   +    .masters        = omap2430_iva_masters,
   +    .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
   +    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
   + };
   + 
 +++ /* Timer Common */
 +++ static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
 +++    .rev_offs       = 0x0000,
 +++    .sysc_offs      = 0x0010,
 +++    .syss_offs      = 0x0014,
 +++    .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 +++                       SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +++                       SYSC_HAS_AUTOIDLE),
 +++    .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +++    .sysc_fields    = &omap_hwmod_sysc_type1,
 +++ };
 +++ 
 +++ static struct omap_hwmod_class omap2430_timer_hwmod_class = {
 +++    .name = "timer",
 +++    .sysc = &omap2430_timer_sysc,
 +++    .rev = OMAP_TIMER_IP_VERSION_1,
 +++ };
 +++ 
 +++ /* timer1 */
 +++ static struct omap_hwmod omap2430_timer1_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
 +++    { .irq = 37, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 +++    {
 +++            .pa_start       = 0x49018000,
 +++            .pa_end         = 0x49018000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_wkup -> timer1 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 +++    .master         = &omap2430_l4_wkup_hwmod,
 +++    .slave          = &omap2430_timer1_hwmod,
 +++    .clk            = "gpt1_ick",
 +++    .addr           = omap2430_timer1_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer1 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 +++    &omap2430_l4_wkup__timer1,
 +++ };
 +++ 
 +++ /* timer1 hwmod */
 +++ static struct omap_hwmod omap2430_timer1_hwmod = {
 +++    .name           = "timer1",
 +++    .mpu_irqs       = omap2430_timer1_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
 +++    .main_clk       = "gpt1_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 +++                    .module_offs = WKUP_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer1_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer2 */
 +++ static struct omap_hwmod omap2430_timer2_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
 +++    { .irq = 38, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4802a000,
 +++            .pa_end         = 0x4802a000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer2 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer2_hwmod,
 +++    .clk            = "gpt2_ick",
 +++    .addr           = omap2430_timer2_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer2 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 +++    &omap2430_l4_core__timer2,
 +++ };
 +++ 
 +++ /* timer2 hwmod */
 +++ static struct omap_hwmod omap2430_timer2_hwmod = {
 +++    .name           = "timer2",
 +++    .mpu_irqs       = omap2430_timer2_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
 +++    .main_clk       = "gpt2_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer2_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer3 */
 +++ static struct omap_hwmod omap2430_timer3_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
 +++    { .irq = 39, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48078000,
 +++            .pa_end         = 0x48078000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer3 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer3_hwmod,
 +++    .clk            = "gpt3_ick",
 +++    .addr           = omap2430_timer3_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer3 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 +++    &omap2430_l4_core__timer3,
 +++ };
 +++ 
 +++ /* timer3 hwmod */
 +++ static struct omap_hwmod omap2430_timer3_hwmod = {
 +++    .name           = "timer3",
 +++    .mpu_irqs       = omap2430_timer3_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
 +++    .main_clk       = "gpt3_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer3_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer4 */
 +++ static struct omap_hwmod omap2430_timer4_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
 +++    { .irq = 40, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4807a000,
 +++            .pa_end         = 0x4807a000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer4 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer4_hwmod,
 +++    .clk            = "gpt4_ick",
 +++    .addr           = omap2430_timer4_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer4 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 +++    &omap2430_l4_core__timer4,
 +++ };
 +++ 
 +++ /* timer4 hwmod */
 +++ static struct omap_hwmod omap2430_timer4_hwmod = {
 +++    .name           = "timer4",
 +++    .mpu_irqs       = omap2430_timer4_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
 +++    .main_clk       = "gpt4_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer4_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer5 */
 +++ static struct omap_hwmod omap2430_timer5_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
 +++    { .irq = 41, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4807c000,
 +++            .pa_end         = 0x4807c000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer5 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer5_hwmod,
 +++    .clk            = "gpt5_ick",
 +++    .addr           = omap2430_timer5_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer5 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 +++    &omap2430_l4_core__timer5,
 +++ };
 +++ 
 +++ /* timer5 hwmod */
 +++ static struct omap_hwmod omap2430_timer5_hwmod = {
 +++    .name           = "timer5",
 +++    .mpu_irqs       = omap2430_timer5_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
 +++    .main_clk       = "gpt5_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer5_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer6 */
 +++ static struct omap_hwmod omap2430_timer6_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
 +++    { .irq = 42, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4807e000,
 +++            .pa_end         = 0x4807e000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer6 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer6_hwmod,
 +++    .clk            = "gpt6_ick",
 +++    .addr           = omap2430_timer6_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer6 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 +++    &omap2430_l4_core__timer6,
 +++ };
 +++ 
 +++ /* timer6 hwmod */
 +++ static struct omap_hwmod omap2430_timer6_hwmod = {
 +++    .name           = "timer6",
 +++    .mpu_irqs       = omap2430_timer6_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
 +++    .main_clk       = "gpt6_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer6_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer7 */
 +++ static struct omap_hwmod omap2430_timer7_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
 +++    { .irq = 43, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48080000,
 +++            .pa_end         = 0x48080000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer7 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer7_hwmod,
 +++    .clk            = "gpt7_ick",
 +++    .addr           = omap2430_timer7_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer7 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 +++    &omap2430_l4_core__timer7,
 +++ };
 +++ 
 +++ /* timer7 hwmod */
 +++ static struct omap_hwmod omap2430_timer7_hwmod = {
 +++    .name           = "timer7",
 +++    .mpu_irqs       = omap2430_timer7_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
 +++    .main_clk       = "gpt7_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer7_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer8 */
 +++ static struct omap_hwmod omap2430_timer8_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
 +++    { .irq = 44, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48082000,
 +++            .pa_end         = 0x48082000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer8 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer8_hwmod,
 +++    .clk            = "gpt8_ick",
 +++    .addr           = omap2430_timer8_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer8 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 +++    &omap2430_l4_core__timer8,
 +++ };
 +++ 
 +++ /* timer8 hwmod */
 +++ static struct omap_hwmod omap2430_timer8_hwmod = {
 +++    .name           = "timer8",
 +++    .mpu_irqs       = omap2430_timer8_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
 +++    .main_clk       = "gpt8_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer8_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer9 */
 +++ static struct omap_hwmod omap2430_timer9_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
 +++    { .irq = 45, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48084000,
 +++            .pa_end         = 0x48084000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer9 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer9_hwmod,
 +++    .clk            = "gpt9_ick",
 +++    .addr           = omap2430_timer9_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer9 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 +++    &omap2430_l4_core__timer9,
 +++ };
 +++ 
 +++ /* timer9 hwmod */
 +++ static struct omap_hwmod omap2430_timer9_hwmod = {
 +++    .name           = "timer9",
 +++    .mpu_irqs       = omap2430_timer9_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
 +++    .main_clk       = "gpt9_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer9_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer10 */
 +++ static struct omap_hwmod omap2430_timer10_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
 +++    { .irq = 46, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48086000,
 +++            .pa_end         = 0x48086000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer10 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer10_hwmod,
 +++    .clk            = "gpt10_ick",
 +++    .addr           = omap2430_timer10_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer10 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 +++    &omap2430_l4_core__timer10,
 +++ };
 +++ 
 +++ /* timer10 hwmod */
 +++ static struct omap_hwmod omap2430_timer10_hwmod = {
 +++    .name           = "timer10",
 +++    .mpu_irqs       = omap2430_timer10_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
 +++    .main_clk       = "gpt10_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer10_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer11 */
 +++ static struct omap_hwmod omap2430_timer11_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
 +++    { .irq = 47, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48088000,
 +++            .pa_end         = 0x48088000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer11 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer11_hwmod,
 +++    .clk            = "gpt11_ick",
 +++    .addr           = omap2430_timer11_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer11 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 +++    &omap2430_l4_core__timer11,
 +++ };
 +++ 
 +++ /* timer11 hwmod */
 +++ static struct omap_hwmod omap2430_timer11_hwmod = {
 +++    .name           = "timer11",
 +++    .mpu_irqs       = omap2430_timer11_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
 +++    .main_clk       = "gpt11_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer11_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 +++ };
 +++ 
 +++ /* timer12 */
 +++ static struct omap_hwmod omap2430_timer12_hwmod;
 +++ static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
 +++    { .irq = 48, },
 ++  };
 ++  
   - /*
   -  * IVA2_1 interface data
   -  */
 +++ static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4808a000,
 +++            .pa_end         = 0x4808a000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 ++  
   - /* IVA2 <- L3 interface */
   - static struct omap_hwmod_ocp_if omap2430_l3__iva = {
   -    .master         = &omap2430_l3_main_hwmod,
   -    .slave          = &omap2430_iva_hwmod,
   -    .clk            = "dsp_fck",
 +++ /* l4_core -> timer12 */
 +++ static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
 +++    .master         = &omap2430_l4_core_hwmod,
 +++    .slave          = &omap2430_timer12_hwmod,
 +++    .clk            = "gpt12_ick",
 +++    .addr           = omap2430_timer12_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
 ++     .user           = OCP_USER_MPU | OCP_USER_SDMA,
 ++  };
 ++  
   - static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
   -    &omap2430_l3__iva,
 +++ /* timer12 slave port */
 +++ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 +++    &omap2430_l4_core__timer12,
 ++  };
 ++  
   - /*
   -  * IVA2 (IVA2)
   -  */
   - 
   - static struct omap_hwmod omap2430_iva_hwmod = {
   -    .name           = "iva",
   -    .class          = &iva_hwmod_class,
   -    .masters        = omap2430_iva_masters,
   -    .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 +++ /* timer12 hwmod */
 +++ static struct omap_hwmod omap2430_timer12_hwmod = {
 +++    .name           = "timer12",
 +++    .mpu_irqs       = omap2430_timer12_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
 +++    .main_clk       = "gpt12_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap2430_timer12_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
 +++    .class          = &omap2430_timer_hwmod_class,
 ++     .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 ++  };
 ++  
     /* l4_wkup -> wd_timer2 */
     static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
        {
@@@@@@ -2125,8 -1575,8 -1581,315 -1506,8 -2166,119 +2241,426 @@@@@@ static struct omap_hwmod omap2430_usbhs
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
     };
     
++ ++/*
++ ++ * 'mcbsp' class
++ ++ * multi channel buffered serial port controller
++ ++ */
++ ++
++ ++static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
++ ++   .rev_offs       = 0x007C,
++ ++   .sysc_offs      = 0x008C,
++ ++   .sysc_flags     = (SYSC_HAS_SOFTRESET),
++ ++   .sysc_fields    = &omap_hwmod_sysc_type1,
++ ++};
++ ++
++ ++static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
++ ++   .name = "mcbsp",
++ ++   .sysc = &omap2430_mcbsp_sysc,
++ ++   .rev  = MCBSP_CONFIG_TYPE2,
++ ++};
 + ++
++ ++/* mcbsp1 */
++ ++static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
++ ++   { .name = "tx",         .irq = 59 },
++ ++   { .name = "rx",         .irq = 60 },
++ ++   { .name = "ovr",        .irq = 61 },
++ ++   { .name = "common",     .irq = 64 },
++ ++};
++ ++
++ ++static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 32 },
++ ++   { .name = "tx", .dma_req = 31 },
++ ++};
++ ++
++ ++static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x48074000,
++ ++           .pa_end         = 0x480740ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
++ ++};
++ ++
++ ++/* l4_core -> mcbsp1 */
++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
++ ++   .master         = &omap2430_l4_core_hwmod,
++ ++   .slave          = &omap2430_mcbsp1_hwmod,
++ ++   .clk            = "mcbsp1_ick",
++ ++   .addr           = omap2430_mcbsp1_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp1 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
++ ++   &omap2430_l4_core__mcbsp1,
++ ++};
++ ++
++ ++static struct omap_hwmod omap2430_mcbsp1_hwmod = {
++ ++   .name           = "mcbsp1",
++ ++   .class          = &omap2430_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap2430_mcbsp1_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
++ ++   .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
++ ++   .main_clk       = "mcbsp1_fck",
++ ++   .prcm           = {
++ ++           .omap2 = {
++ ++                   .prcm_reg_id = 1,
++ ++                   .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
++ ++                   .module_offs = CORE_MOD,
++ ++                   .idlest_reg_id = 1,
++ ++                   .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
++ ++           },
++ ++   },
++ ++   .slaves         = omap2430_mcbsp1_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
++ ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++ ++};
++ ++
++ ++/* mcbsp2 */
++ ++static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
++ ++   { .name = "tx",         .irq = 62 },
++ ++   { .name = "rx",         .irq = 63 },
++ ++   { .name = "common",     .irq = 16 },
++ ++};
++ ++
++ ++static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 34 },
++ ++   { .name = "tx", .dma_req = 33 },
++ ++};
++ ++
++ ++static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x48076000,
++ ++           .pa_end         = 0x480760ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
++ ++};
++ ++
++ ++/* l4_core -> mcbsp2 */
++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
++ ++   .master         = &omap2430_l4_core_hwmod,
++ ++   .slave          = &omap2430_mcbsp2_hwmod,
++ ++   .clk            = "mcbsp2_ick",
++ ++   .addr           = omap2430_mcbsp2_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp2 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
++ ++   &omap2430_l4_core__mcbsp2,
++ ++};
++ ++
++ ++static struct omap_hwmod omap2430_mcbsp2_hwmod = {
++ ++   .name           = "mcbsp2",
++ ++   .class          = &omap2430_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap2430_mcbsp2_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
++ ++   .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
++ ++   .main_clk       = "mcbsp2_fck",
++ ++   .prcm           = {
++ ++           .omap2 = {
++ ++                   .prcm_reg_id = 1,
++ ++                   .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
++ ++                   .module_offs = CORE_MOD,
++ ++                   .idlest_reg_id = 1,
++ ++                   .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
++ ++           },
++ ++   },
++ ++   .slaves         = omap2430_mcbsp2_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
++ ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++ ++};
++ ++
++ ++/* mcbsp3 */
++ ++static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
++ ++   { .name = "tx",         .irq = 89 },
++ ++   { .name = "rx",         .irq = 90 },
++ ++   { .name = "common",     .irq = 17 },
++ ++};
++ ++
++ ++static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 18 },
++ ++   { .name = "tx", .dma_req = 17 },
++ ++};
++ ++
++ ++static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x4808C000,
++ ++           .pa_end         = 0x4808C0ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
++ ++};
++ ++
++ ++/* l4_core -> mcbsp3 */
++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
++ ++   .master         = &omap2430_l4_core_hwmod,
++ ++   .slave          = &omap2430_mcbsp3_hwmod,
++ ++   .clk            = "mcbsp3_ick",
++ ++   .addr           = omap2430_mcbsp3_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp3 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
++ ++   &omap2430_l4_core__mcbsp3,
++ ++};
++ + 
++ ++static struct omap_hwmod omap2430_mcbsp3_hwmod = {
++ ++   .name           = "mcbsp3",
++ ++   .class          = &omap2430_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap2430_mcbsp3_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
++ ++   .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
++ ++   .main_clk       = "mcbsp3_fck",
++ ++   .prcm           = {
++ ++           .omap2 = {
++ ++                   .prcm_reg_id = 1,
++ ++                   .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
++ ++                   .module_offs = CORE_MOD,
++ ++                   .idlest_reg_id = 2,
++ ++                   .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
++ ++           },
++ ++   },
++ ++   .slaves         = omap2430_mcbsp3_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
++ ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++ ++};
++ ++
++ ++/* mcbsp4 */
++ ++static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
++ ++   { .name = "tx",         .irq = 54 },
++ ++   { .name = "rx",         .irq = 55 },
++ ++   { .name = "common",     .irq = 18 },
++ ++};
++ ++
++ ++static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 20 },
++ ++   { .name = "tx", .dma_req = 19 },
++ ++};
++ ++
++ ++static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x4808E000,
++ ++           .pa_end         = 0x4808E0ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
++ ++};
++ ++
++ ++/* l4_core -> mcbsp4 */
++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
++ ++   .master         = &omap2430_l4_core_hwmod,
++ ++   .slave          = &omap2430_mcbsp4_hwmod,
++ ++   .clk            = "mcbsp4_ick",
++ ++   .addr           = omap2430_mcbsp4_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp4 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
++ ++   &omap2430_l4_core__mcbsp4,
++ ++};
++ ++
++ ++static struct omap_hwmod omap2430_mcbsp4_hwmod = {
++ ++   .name           = "mcbsp4",
++ ++   .class          = &omap2430_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap2430_mcbsp4_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
++ ++   .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
++ ++   .main_clk       = "mcbsp4_fck",
++ ++   .prcm           = {
++ ++           .omap2 = {
++ ++                   .prcm_reg_id = 1,
++ ++                   .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
++ ++                   .module_offs = CORE_MOD,
++ ++                   .idlest_reg_id = 2,
++ ++                   .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
++ ++           },
++ ++   },
++ ++   .slaves         = omap2430_mcbsp4_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
++ ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++ ++};
++ ++
++ ++/* mcbsp5 */
++ ++static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
++ ++   { .name = "tx",         .irq = 81 },
++ ++   { .name = "rx",         .irq = 82 },
++ ++   { .name = "common",     .irq = 19 },
++ ++};
++ ++
++ ++static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 22 },
++ ++   { .name = "tx", .dma_req = 21 },
++ ++};
++ ++
++ ++static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x48096000,
++ ++           .pa_end         = 0x480960ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
++ ++};
++ ++
++ ++/* l4_core -> mcbsp5 */
++ ++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
++ ++   .master         = &omap2430_l4_core_hwmod,
++ ++   .slave          = &omap2430_mcbsp5_hwmod,
++ ++   .clk            = "mcbsp5_ick",
++ ++   .addr           = omap2430_mcbsp5_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp5 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
++ ++   &omap2430_l4_core__mcbsp5,
++ ++};
++ ++
++ ++static struct omap_hwmod omap2430_mcbsp5_hwmod = {
++ ++   .name           = "mcbsp5",
++ ++   .class          = &omap2430_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap2430_mcbsp5_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
++ ++   .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
++ ++   .main_clk       = "mcbsp5_fck",
++ ++   .prcm           = {
++ ++           .omap2 = {
++ ++                   .prcm_reg_id = 1,
++ ++                   .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
++ ++                   .module_offs = CORE_MOD,
++ ++                   .idlest_reg_id = 2,
++ ++                   .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
++ ++           },
++ ++   },
++ ++   .slaves         = omap2430_mcbsp5_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
++ ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++ ++};
++ + 
++++ /* MMC/SD/SDIO common */
+ ++ 
++++ static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
++++    .rev_offs       = 0x1fc,
++++    .sysc_offs      = 0x10,
++++    .syss_offs      = 0x14,
++++    .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++++                       SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++++                       SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++++    .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++++    .sysc_fields    = &omap_hwmod_sysc_type1,
++++ };
++++ 
++++ static struct omap_hwmod_class omap2430_mmc_class = {
++++    .name = "mmc",
++++    .sysc = &omap2430_mmc_sysc,
++++ };
++++ 
++++ /* MMC/SD/SDIO1 */
++++ 
++++ static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
++++    { .irq = 83 },
++++ };
++++ 
++++ static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
++++    { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
++++    { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
++++ };
++++ 
++++ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
++++    { .role = "dbck", .clk = "mmchsdb1_fck" },
++++ };
++++ 
++++ static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
++++    &omap2430_l4_core__mmc1,
++++ };
++++ 
++++ static struct omap_mmc_dev_attr mmc1_dev_attr = {
++++    .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
++++ };
++++ 
++++ static struct omap_hwmod omap2430_mmc1_hwmod = {
++++    .name           = "mmc1",
++++    .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
++++    .mpu_irqs       = omap2430_mmc1_mpu_irqs,
++++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
++++    .sdma_reqs      = omap2430_mmc1_sdma_reqs,
++++    .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
++++    .opt_clks       = omap2430_mmc1_opt_clks,
++++    .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
++++    .main_clk       = "mmchs1_fck",
++++    .prcm           = {
++++            .omap2 = {
++++                    .module_offs = CORE_MOD,
++++                    .prcm_reg_id = 2,
++++                    .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
++++                    .idlest_reg_id = 2,
++++                    .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
++++            },
++++    },
++++    .dev_attr       = &mmc1_dev_attr,
++++    .slaves         = omap2430_mmc1_slaves,
++++    .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
++++    .class          = &omap2430_mmc_class,
++++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++++ };
++++ 
++++ /* MMC/SD/SDIO2 */
++++ 
++++ static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
++++    { .irq = 86 },
++++ };
++++ 
++++ static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
++++    { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
++++    { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
++++ };
++++ 
++++ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
++++    { .role = "dbck", .clk = "mmchsdb2_fck" },
++++ };
++++ 
++++ static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
++++    &omap2430_l4_core__mmc2,
++++ };
+++  
++++ static struct omap_hwmod omap2430_mmc2_hwmod = {
++++    .name           = "mmc2",
++++    .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
++++    .mpu_irqs       = omap2430_mmc2_mpu_irqs,
++++    .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
++++    .sdma_reqs      = omap2430_mmc2_sdma_reqs,
++++    .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
++++    .opt_clks       = omap2430_mmc2_opt_clks,
++++    .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
++++    .main_clk       = "mmchs2_fck",
++++    .prcm           = {
++++            .omap2 = {
++++                    .module_offs = CORE_MOD,
++++                    .prcm_reg_id = 2,
++++                    .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
++++                    .idlest_reg_id = 2,
++++                    .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
++++            },
++++    },
++++    .slaves         = omap2430_mmc2_slaves,
++++    .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
++++    .class          = &omap2430_mmc_class,
++++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++++ };
  +  
     static __initdata struct omap_hwmod *omap2430_hwmods[] = {
        &omap2430_l3_main_hwmod,
        &omap2430_l4_core_hwmod,
@@@@@@ -2170,6 -1606,9 -1919,16 -1537,6 -2324,6 +2706,16 @@@@@@
        /* dma_system class*/
        &omap2430_dma_system_hwmod,
     
++ ++   /* mcbsp class */
++ ++   &omap2430_mcbsp1_hwmod,
++ ++   &omap2430_mcbsp2_hwmod,
++ ++   &omap2430_mcbsp3_hwmod,
++ ++   &omap2430_mcbsp4_hwmod,
++ ++   &omap2430_mcbsp5_hwmod,
++ ++
+  ++   /* mailbox class */
+  ++   &omap2430_mailbox_hwmod,
+  ++
        /* mcspi class */
        &omap2430_mcspi1_hwmod,
        &omap2430_mcspi2_hwmod,

diff --cc arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index fc1b2b963bb9cfadab37ec074451861783fc5bb0,510d5e11a4eaecc4560d6c032ba90c1ee7614501,25226bf063e16eeb3064dbbd4517a3b81a3d414a,e9d001228568f1f59c5e66b43b8aaff5c7f46783,5fdcc1e9d4ace7435033771d476c38a669e7a247..e2792cf9c54dfdb8303c4e1990a5e6eed1809423
--- 1/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- 3/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- 4/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- 5/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@@@@@ -22,9 -22,8 -22,9 -22,8 -22,10 +22,11 @@@@@@
     #include <plat/l4_3xxx.h>
     #include <plat/i2c.h>
     #include <plat/gpio.h>
++++ #include <plat/mmc.h>
     #include <plat/smartreflex.h>
++ ++#include <plat/mcbsp.h>
     #include <plat/mcspi.h>
 +++ #include <plat/dmtimer.h>
     
     #include "omap_hwmod_common_data.h"
     
@@@@@@ -516,1175 -515,541 -524,541 -515,541 -577,1175 +586,1175 @@@@@@ static struct omap_hwmod omap3xxx_iva_h
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
     };
     
 -   /* l4_wkup -> wd_timer2 */
 -   static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 -      {
 -              .pa_start       = 0x48314000,
 -              .pa_end         = 0x4831407f,
 -              .flags          = ADDR_TYPE_RT
 -      },
 +++ /* timer class */
 +++ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 +++    .rev_offs       = 0x0000,
 +++    .sysc_offs      = 0x0010,
 +++    .syss_offs      = 0x0014,
 +++    .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 +++                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +++                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 +++    .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +++    .sysc_fields    = &omap_hwmod_sysc_type1,
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 -      .master         = &omap3xxx_l4_wkup_hwmod,
 -      .slave          = &omap3xxx_wd_timer2_hwmod,
 -      .clk            = "wdt2_ick",
 -      .addr           = omap3xxx_wd_timer2_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 -      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 +++    .name = "timer",
 +++    .sysc = &omap3xxx_timer_1ms_sysc,
 +++    .rev = OMAP_TIMER_IP_VERSION_1,
  ++ };
  ++ 
 -   /*
 -    * 'wd_timer' class
 -    * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 -    * overflow condition
 -    */
 -   
 -   static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 +++ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
  ++    .rev_offs       = 0x0000,
  ++    .sysc_offs      = 0x0010,
  ++    .syss_offs      = 0x0014,
 -      .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 -                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 -                         SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 +++    .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 +++                       SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  ++    .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 -      .sysc_fields    = &omap_hwmod_sysc_type1,
 +++    .sysc_fields    = &omap_hwmod_sysc_type1,
  ++ };
  ++ 
 -   /* I2C common */
 -   static struct omap_hwmod_class_sysconfig i2c_sysc = {
 -      .rev_offs       = 0x00,
 -      .sysc_offs      = 0x20,
 -      .syss_offs      = 0x10,
 -      .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 -                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 -                         SYSC_HAS_AUTOIDLE),
 -      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 -      .sysc_fields    = &omap_hwmod_sysc_type1,
 +++ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 +++    .name = "timer",
 +++    .sysc = &omap3xxx_timer_sysc,
 +++    .rev =  OMAP_TIMER_IP_VERSION_1,
  ++ };
  ++ 
 -   static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 -      .name           = "wd_timer",
 -      .sysc           = &omap3xxx_wd_timer_sysc,
 -      .pre_shutdown   = &omap2_wd_timer_disable
 +++ /* timer1 */
 +++ static struct omap_hwmod omap3xxx_timer1_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
 +++    { .irq = 37, },
  ++ };
  ++ 
 -   /* wd_timer2 */
 -   static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 -      &omap3xxx_l4_wkup__wd_timer2,
 +++ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48318000,
 +++            .pa_end         = 0x48318000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 -      .name           = "wd_timer2",
 -      .class          = &omap3xxx_wd_timer_hwmod_class,
 -      .main_clk       = "wdt2_fck",
 +++ /* l4_wkup -> timer1 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 +++    .master         = &omap3xxx_l4_wkup_hwmod,
 +++    .slave          = &omap3xxx_timer1_hwmod,
 +++    .clk            = "gpt1_ick",
 +++    .addr           = omap3xxx_timer1_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer1 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 +++    &omap3xxx_l4_wkup__timer1,
 +++ };
 +++ 
 +++ /* timer1 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer1_hwmod = {
 +++    .name           = "timer1",
 +++    .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
 +++    .main_clk       = "gpt1_fck",
  ++    .prcm           = {
  ++            .omap2 = {
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_WDT2_SHIFT,
 +++                    .module_bit = OMAP3430_EN_GPT1_SHIFT,
  ++                    .module_offs = WKUP_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_wd_timer2_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +++    .slaves         = omap3xxx_timer1_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 +++    .class          = &omap3xxx_timer_1ms_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /* UART common */
 +++ /* timer2 */
 +++ static struct omap_hwmod omap3xxx_timer2_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
 +++    { .irq = 38, },
 +++ };
  ++ 
 -   static struct omap_hwmod_class_sysconfig uart_sysc = {
 -      .rev_offs       = 0x50,
 -      .sysc_offs      = 0x54,
 -      .syss_offs      = 0x58,
 -      .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 -                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 -                         SYSC_HAS_AUTOIDLE),
 -      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 -      .sysc_fields    = &omap_hwmod_sysc_type1,
 +++ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 +++    {
 +++            .pa_start       = 0x49032000,
 +++            .pa_end         = 0x49032000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod_class uart_class = {
 -      .name = "uart",
 -      .sysc = &uart_sysc,
 +++ /* l4_per -> timer2 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer2_hwmod,
 +++    .clk            = "gpt2_ick",
 +++    .addr           = omap3xxx_timer2_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   /* UART1 */
 +++ /* timer2 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 +++    &omap3xxx_l4_per__timer2,
 +++ };
  ++ 
 -   static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 -      { .irq = INT_24XX_UART1_IRQ, },
 +++ /* timer2 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer2_hwmod = {
 +++    .name           = "timer2",
 +++    .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
 +++    .main_clk       = "gpt2_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP3430_EN_GPT2_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap3xxx_timer2_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 +++    .class          = &omap3xxx_timer_1ms_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 -      { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 -      { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 +++ /* timer3 */
 +++ static struct omap_hwmod omap3xxx_timer3_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
 +++    { .irq = 39, },
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 -      &omap3_l4_core__uart1,
 +++ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 +++    {
 +++            .pa_start       = 0x49034000,
 +++            .pa_end         = 0x49034000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_uart1_hwmod = {
 -      .name           = "uart1",
 -      .mpu_irqs       = uart1_mpu_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 -      .sdma_reqs      = uart1_sdma_reqs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 -      .main_clk       = "uart1_fck",
 +++ /* l4_per -> timer3 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer3_hwmod,
 +++    .clk            = "gpt3_ick",
 +++    .addr           = omap3xxx_timer3_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer3 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 +++    &omap3xxx_l4_per__timer3,
 +++ };
 +++ 
 +++ /* timer3 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer3_hwmod = {
 +++    .name           = "timer3",
 +++    .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
 +++    .main_clk       = "gpt3_fck",
  ++    .prcm           = {
  ++            .omap2 = {
 -                      .module_offs = CORE_MOD,
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_UART1_SHIFT,
 +++                    .module_bit = OMAP3430_EN_GPT3_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_uart1_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 -      .class          = &uart_class,
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +++    .slaves         = omap3xxx_timer3_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /* UART2 */
 +++ /* timer4 */
 +++ static struct omap_hwmod omap3xxx_timer4_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
 +++    { .irq = 40, },
 +++ };
  ++ 
 -   static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 -      { .irq = INT_24XX_UART2_IRQ, },
 +++ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 +++    {
 +++            .pa_start       = 0x49036000,
 +++            .pa_end         = 0x49036000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 -      { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 -      { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 +++ /* l4_per -> timer4 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer4_hwmod,
 +++    .clk            = "gpt4_ick",
 +++    .addr           = omap3xxx_timer4_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 -      &omap3_l4_core__uart2,
 +++ /* timer4 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 +++    &omap3xxx_l4_per__timer4,
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_uart2_hwmod = {
 -      .name           = "uart2",
 -      .mpu_irqs       = uart2_mpu_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 -      .sdma_reqs      = uart2_sdma_reqs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 -      .main_clk       = "uart2_fck",
 +++ /* timer4 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer4_hwmod = {
 +++    .name           = "timer4",
 +++    .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
 +++    .main_clk       = "gpt4_fck",
  ++    .prcm           = {
  ++            .omap2 = {
 -                      .module_offs = CORE_MOD,
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_UART2_SHIFT,
 +++                    .module_bit = OMAP3430_EN_GPT4_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_uart2_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 -      .class          = &uart_class,
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +++    .slaves         = omap3xxx_timer4_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /* UART3 */
 +++ /* timer5 */
 +++ static struct omap_hwmod omap3xxx_timer5_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
 +++    { .irq = 41, },
 +++ };
  ++ 
 -   static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 -      { .irq = INT_24XX_UART3_IRQ, },
 +++ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 +++    {
 +++            .pa_start       = 0x49038000,
 +++            .pa_end         = 0x49038000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 -      { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 -      { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 +++ /* l4_per -> timer5 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer5_hwmod,
 +++    .clk            = "gpt5_ick",
 +++    .addr           = omap3xxx_timer5_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 -      &omap3_l4_per__uart3,
 +++ /* timer5 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 +++    &omap3xxx_l4_per__timer5,
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_uart3_hwmod = {
 -      .name           = "uart3",
 -      .mpu_irqs       = uart3_mpu_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 -      .sdma_reqs      = uart3_sdma_reqs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 -      .main_clk       = "uart3_fck",
 +++ /* timer5 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer5_hwmod = {
 +++    .name           = "timer5",
 +++    .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
 +++    .main_clk       = "gpt5_fck",
  ++    .prcm           = {
  ++            .omap2 = {
 -                      .module_offs = OMAP3430_PER_MOD,
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_UART3_SHIFT,
 +++                    .module_bit = OMAP3430_EN_GPT5_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_uart3_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 -      .class          = &uart_class,
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +++    .slaves         = omap3xxx_timer5_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /* UART4 */
 +++ /* timer6 */
 +++ static struct omap_hwmod omap3xxx_timer6_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
 +++    { .irq = 42, },
 +++ };
  ++ 
 -   static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 -      { .irq = INT_36XX_UART4_IRQ, },
 +++ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4903A000,
 +++            .pa_end         = 0x4903A000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 -      { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 -      { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 +++ /* l4_per -> timer6 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer6_hwmod,
 +++    .clk            = "gpt6_ick",
 +++    .addr           = omap3xxx_timer6_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 -      &omap3_l4_per__uart4,
 +++ /* timer6 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 +++    &omap3xxx_l4_per__timer6,
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_uart4_hwmod = {
 -      .name           = "uart4",
 -      .mpu_irqs       = uart4_mpu_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 -      .sdma_reqs      = uart4_sdma_reqs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 -      .main_clk       = "uart4_fck",
 +++ /* timer6 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer6_hwmod = {
 +++    .name           = "timer6",
 +++    .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
 +++    .main_clk       = "gpt6_fck",
  ++    .prcm           = {
  ++            .omap2 = {
 -                      .module_offs = OMAP3430_PER_MOD,
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3630_EN_UART4_SHIFT,
 +++                    .module_bit = OMAP3430_EN_GPT6_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_uart4_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 -      .class          = &uart_class,
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 +++    .slaves         = omap3xxx_timer6_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   static struct omap_hwmod_class i2c_class = {
 -      .name = "i2c",
 -      .sysc = &i2c_sysc,
 +++ /* timer7 */
 +++ static struct omap_hwmod omap3xxx_timer7_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
 +++    { .irq = 43, },
  ++ };
  ++ 
 -   /*
 -    * 'dss' class
 -    * display sub-system
 -    */
 -   
 -   static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
 -      .rev_offs       = 0x0000,
 -      .sysc_offs      = 0x0010,
 -      .syss_offs      = 0x0014,
 -      .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 -      .sysc_fields    = &omap_hwmod_sysc_type1,
 +++ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 +++    {
 +++            .pa_start       = 0x4903C000,
 +++            .pa_end         = 0x4903C000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
 -      .name = "dss",
 -      .sysc = &omap3xxx_dss_sysc,
 +++ /* l4_per -> timer7 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer7_hwmod,
 +++    .clk            = "gpt7_ick",
 +++    .addr           = omap3xxx_timer7_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   /* dss */
 -   static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
 -      { .irq = 25 },
 +++ /* timer7 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 +++    &omap3xxx_l4_per__timer7,
  ++ };
  ++ 
 -   static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 -      { .name = "dispc", .dma_req = 5 },
 -      { .name = "dsi1", .dma_req = 74 },
 +++ /* timer7 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer7_hwmod = {
 +++    .name           = "timer7",
 +++    .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
 +++    .main_clk       = "gpt7_fck",
 +++    .prcm           = {
 +++            .omap2 = {
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP3430_EN_GPT7_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 +++            },
 +++    },
 +++    .slaves         = omap3xxx_timer7_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /* dss */
 -   /* dss master ports */
 -   static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
 -      &omap3xxx_dss__l3,
 +++ /* timer8 */
 +++ static struct omap_hwmod omap3xxx_timer8_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
 +++    { .irq = 44, },
  ++ };
  ++ 
 -   static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
 +++ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
  ++    {
 -              .pa_start       = 0x48050000,
 -              .pa_end         = 0x480503FF,
 +++            .pa_start       = 0x4903E000,
 +++            .pa_end         = 0x4903E000 + SZ_1K - 1,
  ++            .flags          = ADDR_TYPE_RT
  ++    },
  ++ };
  ++ 
 -   /* l4_core -> dss */
 -   static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
 -      .master         = &omap3xxx_l4_core_hwmod,
 -      .slave          = &omap3430es1_dss_core_hwmod,
 -      .clk            = "dss_ick",
 -      .addr           = omap3xxx_dss_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 -      .fw = {
 -              .omap2 = {
 -                      .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
 -                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 -                      .flags  = OMAP_FIREWALL_L4,
 -              }
 -      },
 +++ /* l4_per -> timer8 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer8_hwmod,
 +++    .clk            = "gpt8_ick",
 +++    .addr           = omap3xxx_timer8_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
  ++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
 -      .master         = &omap3xxx_l4_core_hwmod,
 -      .slave          = &omap3xxx_dss_core_hwmod,
 -      .clk            = "dss_ick",
 -      .addr           = omap3xxx_dss_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 -      .fw = {
 +++ /* timer8 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 +++    &omap3xxx_l4_per__timer8,
 +++ };
 +++ 
 +++ /* timer8 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer8_hwmod = {
 +++    .name           = "timer8",
 +++    .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
 +++    .main_clk       = "gpt8_fck",
 +++    .prcm           = {
  ++            .omap2 = {
 -                      .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
 -                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 -                      .flags  = OMAP_FIREWALL_L4,
 -              }
 +++                    .prcm_reg_id = 1,
 +++                    .module_bit = OMAP3430_EN_GPT8_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 +++            },
  ++    },
 -      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++    .slaves         = omap3xxx_timer8_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /* dss slave ports */
 -   static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
 -      &omap3430es1_l4_core__dss,
 +++ /* timer9 */
 +++ static struct omap_hwmod omap3xxx_timer9_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
 +++    { .irq = 45, },
  ++ };
  ++ 
 -   static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 -      &omap3xxx_l4_core__dss,
 +++ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 +++    {
 +++            .pa_start       = 0x49040000,
 +++            .pa_end         = 0x49040000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
  ++ };
  ++ 
 -   static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 -      { .role = "tv_clk", .clk = "dss_tv_fck" },
 -      { .role = "dssclk", .clk = "dss_96m_fck" },
 -      { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 +++ /* l4_per -> timer9 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 +++    .master         = &omap3xxx_l4_per_hwmod,
 +++    .slave          = &omap3xxx_timer9_hwmod,
 +++    .clk            = "gpt9_ick",
 +++    .addr           = omap3xxx_timer9_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 -      .name           = "dss_core",
 -      .class          = &omap3xxx_dss_hwmod_class,
 -      .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 -      .mpu_irqs       = omap3xxx_dss_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 -      .sdma_reqs      = omap3xxx_dss_sdma_chs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 +++ /* timer9 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 +++    &omap3xxx_l4_per__timer9,
 +++ };
  ++ 
 +++ /* timer9 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer9_hwmod = {
 +++    .name           = "timer9",
 +++    .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
 +++    .main_clk       = "gpt9_fck",
  ++    .prcm           = {
  ++            .omap2 = {
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 -                      .module_offs = OMAP3430_DSS_MOD,
 +++                    .module_bit = OMAP3430_EN_GPT9_SHIFT,
 +++                    .module_offs = OMAP3430_PER_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
  ++            },
  ++    },
 -      .opt_clks       = dss_opt_clks,
 -      .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 -      .slaves         = omap3430es1_dss_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
 -      .masters        = omap3xxx_dss_masters,
 -      .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 -      .flags          = HWMOD_NO_IDLEST,
 +++    .slaves         = omap3xxx_timer9_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 -      .name           = "dss_core",
 -      .class          = &omap3xxx_dss_hwmod_class,
 -      .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 -      .mpu_irqs       = omap3xxx_dss_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 -      .sdma_reqs      = omap3xxx_dss_sdma_chs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 +++ /* timer10 */
 +++ static struct omap_hwmod omap3xxx_timer10_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
 +++    { .irq = 46, },
 +++ };
 +++ 
 +++ static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
 +++    {
 +++            .pa_start       = 0x48086000,
 +++            .pa_end         = 0x48086000 + SZ_1K - 1,
 +++            .flags          = ADDR_TYPE_RT
 +++    },
 +++ };
 +++ 
 +++ /* l4_core -> timer10 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
 +++    .master         = &omap3xxx_l4_core_hwmod,
 +++    .slave          = &omap3xxx_timer10_hwmod,
 +++    .clk            = "gpt10_ick",
 +++    .addr           = omap3xxx_timer10_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
 +++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +++ };
 +++ 
 +++ /* timer10 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
 +++    &omap3xxx_l4_core__timer10,
 +++ };
  ++ 
 +++ /* timer10 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer10_hwmod = {
 +++    .name           = "timer10",
 +++    .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
 +++    .main_clk       = "gpt10_fck",
  ++    .prcm           = {
  ++            .omap2 = {
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 -                      .module_offs = OMAP3430_DSS_MOD,
 +++                    .module_bit = OMAP3430_EN_GPT10_SHIFT,
 +++                    .module_offs = CORE_MOD,
  ++                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 -                      .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
  ++            },
  ++    },
 -      .opt_clks       = dss_opt_clks,
 -      .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 -      .slaves         = omap3xxx_dss_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
 -      .masters        = omap3xxx_dss_masters,
 -      .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
 -                              CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 -   };
 -   
 -   /*
 -    * 'dispc' class
 -    * display controller
 -    */
 -   
 -   static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
 -      .rev_offs       = 0x0000,
 -      .sysc_offs      = 0x0010,
 -      .syss_offs      = 0x0014,
 -      .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 -                         SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
 -                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 -      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 -                         MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 -      .sysc_fields    = &omap_hwmod_sysc_type1,
 +++    .slaves         = omap3xxx_timer10_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
 +++    .class          = &omap3xxx_timer_1ms_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
 -      .name = "dispc",
 -      .sysc = &omap3xxx_dispc_sysc,
 +++ /* timer11 */
 +++ static struct omap_hwmod omap3xxx_timer11_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
 +++    { .irq = 47, },
  ++ };
  ++ 
 -   static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
 +++ static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
  ++    {
 -              .pa_start       = 0x48050400,
 -              .pa_end         = 0x480507FF,
 +++            .pa_start       = 0x48088000,
 +++            .pa_end         = 0x48088000 + SZ_1K - 1,
  ++            .flags          = ADDR_TYPE_RT
  ++    },
  ++ };
  ++ 
 -   /* l4_core -> dss_dispc */
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
 +++ /* l4_core -> timer11 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
  ++    .master         = &omap3xxx_l4_core_hwmod,
 -      .slave          = &omap3xxx_dss_dispc_hwmod,
 -      .clk            = "dss_ick",
 -      .addr           = omap3xxx_dss_dispc_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
 -      .fw = {
 -              .omap2 = {
 -                      .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
 -                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 -                      .flags  = OMAP_FIREWALL_L4,
 -              }
 -      },
 +++    .slave          = &omap3xxx_timer11_hwmod,
 +++    .clk            = "gpt11_ick",
 +++    .addr           = omap3xxx_timer11_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
  ++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   /* dss_dispc slave ports */
 -   static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
 -      &omap3xxx_l4_core__dss_dispc,
 +++ /* timer11 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
 +++    &omap3xxx_l4_core__timer11,
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 -      .name           = "dss_dispc",
 -      .class          = &omap3xxx_dispc_hwmod_class,
 -      .main_clk       = "dss1_alwon_fck",
 +++ /* timer11 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer11_hwmod = {
 +++    .name           = "timer11",
 +++    .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
 +++    .main_clk       = "gpt11_fck",
  ++    .prcm           = {
  ++            .omap2 = {
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 -                      .module_offs = OMAP3430_DSS_MOD,
 +++                    .module_bit = OMAP3430_EN_GPT11_SHIFT,
 +++                    .module_offs = CORE_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_dss_dispc_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 -                              CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
 -                              CHIP_GE_OMAP3630ES1_1),
 -      .flags          = HWMOD_NO_IDLEST,
 +++    .slaves         = omap3xxx_timer11_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /*
 -    * 'dsi' class
 -    * display serial interface controller
 -    */
 -   
 -   static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 -      .name = "dsi",
 +++ /* timer12*/
 +++ static struct omap_hwmod omap3xxx_timer12_hwmod;
 +++ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 +++    { .irq = 95, },
  ++ };
  ++ 
 -   /* dss_dsi1 */
 -   static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
 +++ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
  ++    {
 -              .pa_start       = 0x4804FC00,
 -              .pa_end         = 0x4804FFFF,
 +++            .pa_start       = 0x48304000,
 +++            .pa_end         = 0x48304000 + SZ_1K - 1,
  ++            .flags          = ADDR_TYPE_RT
  ++    },
  ++ };
  ++ 
 -   /* l4_core -> dss_dsi1 */
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
 +++ /* l4_core -> timer12 */
 +++ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
  ++    .master         = &omap3xxx_l4_core_hwmod,
 -      .slave          = &omap3xxx_dss_dsi1_hwmod,
 -      .addr           = omap3xxx_dss_dsi1_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
 -      .fw = {
 -              .omap2 = {
 -                      .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
 -                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 -                      .flags  = OMAP_FIREWALL_L4,
 -              }
 -      },
 +++    .slave          = &omap3xxx_timer12_hwmod,
 +++    .clk            = "gpt12_ick",
 +++    .addr           = omap3xxx_timer12_addrs,
 +++    .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
  ++    .user           = OCP_USER_MPU | OCP_USER_SDMA,
  ++ };
  ++ 
 -   /* dss_dsi1 slave ports */
 -   static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
 -      &omap3xxx_l4_core__dss_dsi1,
 +++ /* timer12 slave port */
 +++ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
 +++    &omap3xxx_l4_core__timer12,
  ++ };
  ++ 
 -   static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 -      .name           = "dss_dsi1",
 -      .class          = &omap3xxx_dsi_hwmod_class,
 -      .main_clk       = "dss1_alwon_fck",
 +++ /* timer12 hwmod */
 +++ static struct omap_hwmod omap3xxx_timer12_hwmod = {
 +++    .name           = "timer12",
 +++    .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 +++    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
 +++    .main_clk       = "gpt12_fck",
  ++    .prcm           = {
  ++            .omap2 = {
  ++                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 -                      .module_offs = OMAP3430_DSS_MOD,
 +++                    .module_bit = OMAP3430_EN_GPT12_SHIFT,
 +++                    .module_offs = WKUP_MOD,
 +++                    .idlest_reg_id = 1,
 +++                    .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
  ++            },
  ++    },
 -      .slaves         = omap3xxx_dss_dsi1_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 -                              CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
 -                              CHIP_GE_OMAP3630ES1_1),
 -      .flags          = HWMOD_NO_IDLEST,
 +++    .slaves         = omap3xxx_timer12_slaves,
 +++    .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
 +++    .class          = &omap3xxx_timer_hwmod_class,
 +++    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  ++ };
  ++ 
 -   /*
 -    * 'rfbi' class
 -    * remote frame buffer interface
 -    */
 +   /* l4_wkup -> wd_timer2 */
 +   static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 +      {
 +              .pa_start       = 0x48314000,
 +              .pa_end         = 0x4831407f,
 +              .flags          = ADDR_TYPE_RT
 +      },
 +   };
     
 -   static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
 -      .rev_offs       = 0x0000,
 -      .sysc_offs      = 0x0010,
 -      .syss_offs      = 0x0014,
 -      .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 -                         SYSC_HAS_AUTOIDLE),
 -      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +   static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 +      .master         = &omap3xxx_l4_wkup_hwmod,
 +      .slave          = &omap3xxx_wd_timer2_hwmod,
 +      .clk            = "wdt2_ick",
 +      .addr           = omap3xxx_wd_timer2_addrs,
 +      .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +   };
 +   
 +   /*
 +    * 'wd_timer' class
 +    * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 +    * overflow condition
 +    */
 +   
 +   static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 +      .rev_offs       = 0x0000,
 +      .sysc_offs      = 0x0010,
 +      .syss_offs      = 0x0014,
 +      .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 +                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +                         SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +   };
 +   
 +   /* I2C common */
 +   static struct omap_hwmod_class_sysconfig i2c_sysc = {
 +      .rev_offs       = 0x00,
 +      .sysc_offs      = 0x20,
 +      .syss_offs      = 0x10,
 +      .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 +                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +                         SYSC_HAS_AUTOIDLE),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +   };
 +   
 +   static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 +      .name           = "wd_timer",
 +      .sysc           = &omap3xxx_wd_timer_sysc,
 +      .pre_shutdown   = &omap2_wd_timer_disable
 +   };
 +   
 +   /* wd_timer2 */
 +   static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 +      &omap3xxx_l4_wkup__wd_timer2,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 +      .name           = "wd_timer2",
 +      .class          = &omap3xxx_wd_timer_hwmod_class,
 +      .main_clk       = "wdt2_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_WDT2_SHIFT,
 +                      .module_offs = WKUP_MOD,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 +              },
 +      },
 +      .slaves         = omap3xxx_wd_timer2_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +   };
 +   
 +   /* UART common */
 +   
 +   static struct omap_hwmod_class_sysconfig uart_sysc = {
 +      .rev_offs       = 0x50,
 +      .sysc_offs      = 0x54,
 +      .syss_offs      = 0x58,
 +      .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 +                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 +                         SYSC_HAS_AUTOIDLE),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +   };
 +   
 +   static struct omap_hwmod_class uart_class = {
 +      .name = "uart",
 +      .sysc = &uart_sysc,
 +   };
 +   
 +   /* UART1 */
 +   
 +   static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 +      { .irq = INT_24XX_UART1_IRQ, },
 +   };
 +   
 +   static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 +      { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 +      { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 +   };
 +   
 +   static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 +      &omap3_l4_core__uart1,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_uart1_hwmod = {
 +      .name           = "uart1",
 +      .mpu_irqs       = uart1_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 +      .sdma_reqs      = uart1_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 +      .main_clk       = "uart1_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_UART1_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 +              },
 +      },
 +      .slaves         = omap3xxx_uart1_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 +      .class          = &uart_class,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +   };
 +   
 +   /* UART2 */
 +   
 +   static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 +      { .irq = INT_24XX_UART2_IRQ, },
 +   };
 +   
 +   static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 +      { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 +      { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 +   };
 +   
 +   static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 +      &omap3_l4_core__uart2,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_uart2_hwmod = {
 +      .name           = "uart2",
 +      .mpu_irqs       = uart2_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 +      .sdma_reqs      = uart2_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 +      .main_clk       = "uart2_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = CORE_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_UART2_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 +              },
 +      },
 +      .slaves         = omap3xxx_uart2_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 +      .class          = &uart_class,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +   };
 +   
 +   /* UART3 */
 +   
 +   static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 +      { .irq = INT_24XX_UART3_IRQ, },
 +   };
 +   
 +   static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 +      { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 +      { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 +   };
 +   
 +   static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 +      &omap3_l4_per__uart3,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_uart3_hwmod = {
 +      .name           = "uart3",
 +      .mpu_irqs       = uart3_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 +      .sdma_reqs      = uart3_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 +      .main_clk       = "uart3_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = OMAP3430_PER_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_UART3_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 +              },
 +      },
 +      .slaves         = omap3xxx_uart3_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 +      .class          = &uart_class,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 +   };
 +   
 +   /* UART4 */
 +   
 +   static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 +      { .irq = INT_36XX_UART4_IRQ, },
 +   };
 +   
 +   static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 +      { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 +      { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 +   };
 +   
 +   static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 +      &omap3_l4_per__uart4,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_uart4_hwmod = {
 +      .name           = "uart4",
 +      .mpu_irqs       = uart4_mpu_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 +      .sdma_reqs      = uart4_sdma_reqs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 +      .main_clk       = "uart4_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .module_offs = OMAP3430_PER_MOD,
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3630_EN_UART4_SHIFT,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 +              },
 +      },
 +      .slaves         = omap3xxx_uart4_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 +      .class          = &uart_class,
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 +   };
 +   
 +   static struct omap_hwmod_class i2c_class = {
 +      .name = "i2c",
 +      .sysc = &i2c_sysc,
 +   };
 +   
 +   /*
 +    * 'dss' class
 +    * display sub-system
 +    */
 +   
 +   static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
 +      .rev_offs       = 0x0000,
 +      .sysc_offs      = 0x0010,
 +      .syss_offs      = 0x0014,
 +      .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +   };
 +   
 +   static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
 +      .name = "dss",
 +      .sysc = &omap3xxx_dss_sysc,
 +   };
 +   
 +   /* dss */
 +   static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
 +      { .irq = 25 },
 +   };
 +   
 +   static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 +      { .name = "dispc", .dma_req = 5 },
 +      { .name = "dsi1", .dma_req = 74 },
 +   };
 +   
 +   /* dss */
 +   /* dss master ports */
 +   static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
 +      &omap3xxx_dss__l3,
 +   };
 +   
 +   static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
 +      {
 +              .pa_start       = 0x48050000,
 +              .pa_end         = 0x480503FF,
 +              .flags          = ADDR_TYPE_RT
 +      },
 +   };
 +   
 +   /* l4_core -> dss */
 +   static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap3430es1_dss_core_hwmod,
 +      .clk            = "dss_ick",
 +      .addr           = omap3xxx_dss_addrs,
 +      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 +      .fw = {
 +              .omap2 = {
 +                      .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
 +                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 +                      .flags  = OMAP_FIREWALL_L4,
 +              }
 +      },
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +   };
 +   
 +   static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap3xxx_dss_core_hwmod,
 +      .clk            = "dss_ick",
 +      .addr           = omap3xxx_dss_addrs,
 +      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 +      .fw = {
 +              .omap2 = {
 +                      .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
 +                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 +                      .flags  = OMAP_FIREWALL_L4,
 +              }
 +      },
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +   };
 +   
 +   /* dss slave ports */
 +   static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
 +      &omap3430es1_l4_core__dss,
 +   };
 +   
 +   static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 +      &omap3xxx_l4_core__dss,
 +   };
 +   
 +   static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 +      { .role = "tv_clk", .clk = "dss_tv_fck" },
 +      { .role = "dssclk", .clk = "dss_96m_fck" },
 +      { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 +   };
 +   
 +   static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 +      .name           = "dss_core",
 +      .class          = &omap3xxx_dss_hwmod_class,
 +      .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 +      .mpu_irqs       = omap3xxx_dss_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 +      .sdma_reqs      = omap3xxx_dss_sdma_chs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 +   
 +      .prcm           = {
 +              .omap2 = {
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 +                      .module_offs = OMAP3430_DSS_MOD,
 +                      .idlest_reg_id = 1,
 +                      .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 +              },
 +      },
 +      .opt_clks       = dss_opt_clks,
 +      .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 +      .slaves         = omap3430es1_dss_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
 +      .masters        = omap3xxx_dss_masters,
 +      .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 +      .flags          = HWMOD_NO_IDLEST,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 +      .name           = "dss_core",
 +      .class          = &omap3xxx_dss_hwmod_class,
 +      .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 +      .mpu_irqs       = omap3xxx_dss_irqs,
 +      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 +      .sdma_reqs      = omap3xxx_dss_sdma_chs,
 +      .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 +   
 +      .prcm           = {
 +              .omap2 = {
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 +                      .module_offs = OMAP3430_DSS_MOD,
 +                      .idlest_reg_id = 1,
 +                      .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 +                      .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 +              },
 +      },
 +      .opt_clks       = dss_opt_clks,
 +      .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 +      .slaves         = omap3xxx_dss_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
 +      .masters        = omap3xxx_dss_masters,
 +      .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
 +                              CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 +   };
 +   
 +   /*
 +    * 'dispc' class
 +    * display controller
 +    */
 +   
 +   static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
 +      .rev_offs       = 0x0000,
 +      .sysc_offs      = 0x0010,
 +      .syss_offs      = 0x0014,
 +      .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 +                         SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
 +                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 +                         MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 +      .sysc_fields    = &omap_hwmod_sysc_type1,
 +   };
 +   
 +   static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
 +      .name = "dispc",
 +      .sysc = &omap3xxx_dispc_sysc,
 +   };
 +   
 +   static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
 +      {
 +              .pa_start       = 0x48050400,
 +              .pa_end         = 0x480507FF,
 +              .flags          = ADDR_TYPE_RT
 +      },
 +   };
 +   
 +   /* l4_core -> dss_dispc */
 +   static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap3xxx_dss_dispc_hwmod,
 +      .clk            = "dss_ick",
 +      .addr           = omap3xxx_dss_dispc_addrs,
 +      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
 +      .fw = {
 +              .omap2 = {
 +                      .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
 +                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 +                      .flags  = OMAP_FIREWALL_L4,
 +              }
 +      },
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +   };
 +   
 +   /* dss_dispc slave ports */
 +   static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
 +      &omap3xxx_l4_core__dss_dispc,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 +      .name           = "dss_dispc",
 +      .class          = &omap3xxx_dispc_hwmod_class,
 +      .main_clk       = "dss1_alwon_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 +                      .module_offs = OMAP3430_DSS_MOD,
 +              },
 +      },
 +      .slaves         = omap3xxx_dss_dispc_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 +                              CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
 +                              CHIP_GE_OMAP3630ES1_1),
 +      .flags          = HWMOD_NO_IDLEST,
 +   };
 +   
 +   /*
 +    * 'dsi' class
 +    * display serial interface controller
 +    */
 +   
 +   static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 +      .name = "dsi",
 +   };
 +   
 +   /* dss_dsi1 */
 +   static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
 +      {
 +              .pa_start       = 0x4804FC00,
 +              .pa_end         = 0x4804FFFF,
 +              .flags          = ADDR_TYPE_RT
 +      },
 +   };
 +   
 +   /* l4_core -> dss_dsi1 */
 +   static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
 +      .master         = &omap3xxx_l4_core_hwmod,
 +      .slave          = &omap3xxx_dss_dsi1_hwmod,
 +      .addr           = omap3xxx_dss_dsi1_addrs,
 +      .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
 +      .fw = {
 +              .omap2 = {
 +                      .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
 +                      .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 +                      .flags  = OMAP_FIREWALL_L4,
 +              }
 +      },
 +      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 +   };
 +   
 +   /* dss_dsi1 slave ports */
 +   static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
 +      &omap3xxx_l4_core__dss_dsi1,
 +   };
 +   
 +   static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 +      .name           = "dss_dsi1",
 +      .class          = &omap3xxx_dsi_hwmod_class,
 +      .main_clk       = "dss1_alwon_fck",
 +      .prcm           = {
 +              .omap2 = {
 +                      .prcm_reg_id = 1,
 +                      .module_bit = OMAP3430_EN_DSS1_SHIFT,
 +                      .module_offs = OMAP3430_DSS_MOD,
 +              },
 +      },
 +      .slaves         = omap3xxx_dss_dsi1_slaves,
 +      .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
 +      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 +                              CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
 +                              CHIP_GE_OMAP3630ES1_1),
 +      .flags          = HWMOD_NO_IDLEST,
 +   };
 +   
 +   /*
 +    * 'rfbi' class
 +    * remote frame buffer interface
 +    */
 +   
 +   static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
 +      .rev_offs       = 0x0000,
 +      .sysc_offs      = 0x0010,
 +      .syss_offs      = 0x0014,
 +      .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 +                         SYSC_HAS_AUTOIDLE),
 +      .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
        .sysc_fields    = &omap_hwmod_sysc_type1,
     };
     
@@@@@@ -2200,170 -1208,527 -1574,601 -1565,170 -2261,170 +2270,601 @@@@@@ static struct omap_hwmod omap3xxx_gpio4
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
     };
     
 -   /* I2C2 */
 -   
 -   static struct omap_i2c_dev_attr i2c2_dev_attr = {
 -      .fifo_depth     = 8, /* bytes */
 -   };
 -   
 -   static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 -      { .irq = INT_24XX_I2C2_IRQ, },
   - /* gpio5 */
   - static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
   -    { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
 + + /* gpio5 */
 + + static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 + +    { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
   + };
   + 
 -   static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
 -      { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 -      { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 + + static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 + +    { .role = "dbclk", .clk = "gpio5_dbck", },
   + };
   + 
 -   static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 -      &omap3_l4_core__i2c2,
 + + static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
 + +    &omap3xxx_l4_per__gpio5,
   + };
   + 
 -   static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 -      .name           = "i2c2",
 -      .mpu_irqs       = i2c2_mpu_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
 -      .sdma_reqs      = i2c2_sdma_reqs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
 -      .main_clk       = "i2c2_fck",
 + + static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 + +    .name           = "gpio5",
 + +    .mpu_irqs       = omap3xxx_gpio5_irqs,
 + +    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
 + +    .main_clk       = "gpio5_ick",
 + +    .opt_clks       = gpio5_opt_clks,
 + +    .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
   +    .prcm           = {
   +            .omap2 = {
 -                      .module_offs = CORE_MOD,
   +                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_I2C2_SHIFT,
 + +                    .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 + +                    .module_offs = OMAP3430_PER_MOD,
   +                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 + +                    .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
   +            },
   +    },
 -      .slaves         = omap3xxx_i2c2_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
 -      .class          = &i2c_class,
 -      .dev_attr       = &i2c2_dev_attr,
 + +    .slaves         = omap3xxx_gpio5_slaves,
 + +    .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
 + +    .class          = &omap3xxx_gpio_hwmod_class,
 + +    .dev_attr       = &gpio_dev_attr,
   +    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
   + };
   + 
 -   /* I2C3 */
 -   
 -   static struct omap_i2c_dev_attr i2c3_dev_attr = {
 -      .fifo_depth     = 64, /* bytes */
 -   };
 -   
 -   static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 -      { .irq = INT_34XX_I2C3_IRQ, },
 + + /* gpio6 */
 + + static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
 + +    { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
   + };
   + 
 -   static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 -      { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 -      { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 + + static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 + +    { .role = "dbclk", .clk = "gpio6_dbck", },
   + };
   + 
 -   static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 -      &omap3_l4_core__i2c3,
 + + static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
 + +    &omap3xxx_l4_per__gpio6,
   + };
   + 
 -   static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 -      .name           = "i2c3",
 -      .mpu_irqs       = i2c3_mpu_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
 -      .sdma_reqs      = i2c3_sdma_reqs,
 -      .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
 -      .main_clk       = "i2c3_fck",
 + + static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 + +    .name           = "gpio6",
 + +    .mpu_irqs       = omap3xxx_gpio6_irqs,
 + +    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
 + +    .main_clk       = "gpio6_ick",
 + +    .opt_clks       = gpio6_opt_clks,
 + +    .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
   +    .prcm           = {
   +            .omap2 = {
 -                      .module_offs = CORE_MOD,
   +                    .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_I2C3_SHIFT,
 + +                    .module_bit = OMAP3430_EN_GPIO6_SHIFT,
 + +                    .module_offs = OMAP3430_PER_MOD,
   +                    .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 + +                    .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
   +            },
   +    },
 -      .slaves         = omap3xxx_i2c3_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
 -      .class          = &i2c_class,
 -      .dev_attr       = &i2c3_dev_attr,
 + +    .slaves         = omap3xxx_gpio6_slaves,
 + +    .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
 + +    .class          = &omap3xxx_gpio_hwmod_class,
 + +    .dev_attr       = &gpio_dev_attr,
   +    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
   + };
   + 
 -   /* l4_wkup -> gpio1 */
 -   static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
 -      {
 -              .pa_start       = 0x48310000,
 -              .pa_end         = 0x483101ff,
 -              .flags          = ADDR_TYPE_RT
 -      },
 -   };
 -   
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
 -      .master         = &omap3xxx_l4_wkup_hwmod,
 -      .slave          = &omap3xxx_gpio1_hwmod,
 -      .addr           = omap3xxx_gpio1_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
 + + /* dma_system -> L3 */
 + + static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
 + +    .master         = &omap3xxx_dma_system_hwmod,
 + +    .slave          = &omap3xxx_l3_main_hwmod,
 + +    .clk            = "core_l3_ick",
   +    .user           = OCP_USER_MPU | OCP_USER_SDMA,
   + };
   + 
 -   /* l4_per -> gpio2 */
 -   static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
 -      {
 -              .pa_start       = 0x49050000,
 -              .pa_end         = 0x490501ff,
 -              .flags          = ADDR_TYPE_RT
 -      },
 + + /* dma attributes */
 + + static struct omap_dma_dev_attr dma_dev_attr = {
 + +    .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 + +                            IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 + +    .lch_count = 32,
   + };
   + 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
 -      .master         = &omap3xxx_l4_per_hwmod,
 -      .slave          = &omap3xxx_gpio2_hwmod,
 -      .addr           = omap3xxx_gpio2_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
 -      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 + + static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 + +    .rev_offs       = 0x0000,
 + +    .sysc_offs      = 0x002c,
 + +    .syss_offs      = 0x0028,
 + +    .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 + +                       SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 + +                       SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 + +    .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 + +                       MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 + +    .sysc_fields    = &omap_hwmod_sysc_type1,
   + };
   + 
 -   /* l4_per -> gpio3 */
 -   static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
 -      {
 -              .pa_start       = 0x49052000,
 -              .pa_end         = 0x490521ff,
 -              .flags          = ADDR_TYPE_RT
 -      },
 + + static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 + +    .name = "dma",
 + +    .sysc = &omap3xxx_dma_sysc,
   + };
   + 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
 -      .master         = &omap3xxx_l4_per_hwmod,
 -      .slave          = &omap3xxx_gpio3_hwmod,
 -      .addr           = omap3xxx_gpio3_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
 -      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 + + /* dma_system */
 + + static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
 + +    { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
 + +    { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
 + +    { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
 + +    { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
   + };
   + 
 -   /* l4_per -> gpio4 */
 -   static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
 + + static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
   +    {
 -              .pa_start       = 0x49054000,
 -              .pa_end         = 0x490541ff,
 + +            .pa_start       = 0x48056000,
 + +            .pa_end         = 0x4a0560ff,
   +            .flags          = ADDR_TYPE_RT
   +    },
   + };
   + 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
 -      .master         = &omap3xxx_l4_per_hwmod,
 -      .slave          = &omap3xxx_gpio4_hwmod,
 -      .addr           = omap3xxx_gpio4_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
 -      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 -   };
 -   
 -   /* l4_per -> gpio5 */
 -   static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
 -      {
 -              .pa_start       = 0x49056000,
 -              .pa_end         = 0x490561ff,
 -              .flags          = ADDR_TYPE_RT
 -      },
 + + /* dma_system master ports */
 + + static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
 + +    &omap3xxx_dma_system__l3,
   + };
   + 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
 -      .master         = &omap3xxx_l4_per_hwmod,
 -      .slave          = &omap3xxx_gpio5_hwmod,
 -      .addr           = omap3xxx_gpio5_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
 + + /* l4_cfg -> dma_system */
 + + static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
 + +    .master         = &omap3xxx_l4_core_hwmod,
 + +    .slave          = &omap3xxx_dma_system_hwmod,
 + +    .clk            = "core_l4_ick",
 + +    .addr           = omap3xxx_dma_system_addrs,
 + +    .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
   +    .user           = OCP_USER_MPU | OCP_USER_SDMA,
   + };
   + 
 -   /* l4_per -> gpio6 */
 -   static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
 -      {
 -              .pa_start       = 0x49058000,
 -              .pa_end         = 0x490581ff,
 -              .flags          = ADDR_TYPE_RT
 -      },
 + + /* dma_system slave ports */
 + + static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
 + +    &omap3xxx_l4_core__dma_system,
   + };
   + 
 -   static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
 -      .master         = &omap3xxx_l4_per_hwmod,
 -      .slave          = &omap3xxx_gpio6_hwmod,
 -      .addr           = omap3xxx_gpio6_addrs,
 -      .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
 -      .user           = OCP_USER_MPU | OCP_USER_SDMA,
 + + static struct omap_hwmod omap3xxx_dma_system_hwmod = {
 + +    .name           = "dma",
 + +    .class          = &omap3xxx_dma_hwmod_class,
 + +    .mpu_irqs       = omap3xxx_dma_system_irqs,
 + +    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
 + +    .main_clk       = "core_l3_ick",
 + +    .prcm = {
 + +            .omap2 = {
 + +                    .module_offs            = CORE_MOD,
 + +                    .prcm_reg_id            = 1,
 + +                    .module_bit             = OMAP3430_ST_SDMA_SHIFT,
 + +                    .idlest_reg_id          = 1,
 + +                    .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
 + +            },
 + +    },
 + +    .slaves         = omap3xxx_dma_system_slaves,
 + +    .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
 + +    .masters        = omap3xxx_dma_system_masters,
 + +    .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
 + +    .dev_attr       = &dma_dev_attr,
 + +    .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 + +    .flags          = HWMOD_NO_IDLEST,
   + };
   + 
+  ++/*
 -    * 'gpio' class
 -    * general purpose io module
++ ++ * 'mcbsp' class
++ ++ * multi channel buffered serial port controller
+  ++ */
+  ++
 -   static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 -      .rev_offs       = 0x0000,
 -      .sysc_offs      = 0x0010,
 -      .syss_offs      = 0x0014,
 -      .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 -                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ ++static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
++ ++   .sysc_offs      = 0x008c,
++ ++   .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
++ ++                      SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+  ++   .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 -      .sysc_fields    = &omap_hwmod_sysc_type1,
++ ++   .sysc_fields    = &omap_hwmod_sysc_type1,
++ ++   .clockact       = 0x2,
+  ++};
+  ++
 -   static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 -      .name = "gpio",
 -      .sysc = &omap3xxx_gpio_sysc,
 -      .rev = 1,
++ ++static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
++ ++   .name = "mcbsp",
++ ++   .sysc = &omap3xxx_mcbsp_sysc,
++ ++   .rev  = MCBSP_CONFIG_TYPE3,
+  ++};
+  ++
 -   /* gpio_dev_attr*/
 -   static struct omap_gpio_dev_attr gpio_dev_attr = {
 -      .bank_width = 32,
 -      .dbck_flag = true,
++ ++/* mcbsp1 */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
++ ++   { .name = "irq", .irq = 16 },
++ ++   { .name = "tx", .irq = 59 },
++ ++   { .name = "rx", .irq = 60 },
+  ++};
+  ++
 -   /* gpio1 */
 -   static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
 -      { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 32 },
++ ++   { .name = "tx", .dma_req = 31 },
+  ++};
+  ++
 -   static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 -      { .role = "dbclk", .clk = "gpio1_dbck", },
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x48074000,
++ ++           .pa_end         = 0x480740ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
+  ++};
+  ++
 -   static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
 -      &omap3xxx_l4_wkup__gpio1,
++ ++/* l4_core -> mcbsp1 */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
++ ++   .master         = &omap3xxx_l4_core_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp1_hwmod,
++ ++   .clk            = "mcbsp1_ick",
++ ++   .addr           = omap3xxx_mcbsp1_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
+  ++};
+  ++
 -   static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 -      .name           = "gpio1",
 -      .mpu_irqs       = omap3xxx_gpio1_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
 -      .main_clk       = "gpio1_ick",
 -      .opt_clks       = gpio1_opt_clks,
 -      .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
++ ++/* mcbsp1 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
++ ++   &omap3xxx_l4_core__mcbsp1,
++ ++};
++ ++
++ ++static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
++ ++   .name           = "mcbsp1",
++ ++   .class          = &omap3xxx_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp1_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
++ ++   .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
++ ++   .main_clk       = "mcbsp1_fck",
+  ++   .prcm           = {
+  ++           .omap2 = {
+  ++                   .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 -                      .module_offs = WKUP_MOD,
++ ++                   .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
++ ++                   .module_offs = CORE_MOD,
+  ++                   .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
+  ++           },
+  ++   },
 -      .slaves         = omap3xxx_gpio1_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
 -      .class          = &omap3xxx_gpio_hwmod_class,
 -      .dev_attr       = &gpio_dev_attr,
++ ++   .slaves         = omap3xxx_mcbsp1_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
+  ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+  ++};
+  ++
 -   /* gpio2 */
 -   static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
 -      { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
 -   };
 -   
 -   static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 -      { .role = "dbclk", .clk = "gpio2_dbck", },
++ ++/* mcbsp2 */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
++ ++   { .name = "irq", .irq = 17 },
++ ++   { .name = "tx", .irq = 62 },
++ ++   { .name = "rx", .irq = 63 },
+  ++};
+  ++
 -   static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
 -      &omap3xxx_l4_per__gpio2,
++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 34 },
++ ++   { .name = "tx", .dma_req = 33 },
+  ++};
+  ++
 -   static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 -      .name           = "gpio2",
 -      .mpu_irqs       = omap3xxx_gpio2_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
 -      .main_clk       = "gpio2_ick",
 -      .opt_clks       = gpio2_opt_clks,
 -      .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 -      .prcm           = {
 -              .omap2 = {
 -                      .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 -                      .module_offs = OMAP3430_PER_MOD,
 -                      .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 -              },
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x49022000,
++ ++           .pa_end         = 0x490220ff,
++ ++           .flags          = ADDR_TYPE_RT
+  ++   },
 -      .slaves         = omap3xxx_gpio2_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
 -      .class          = &omap3xxx_gpio_hwmod_class,
 -      .dev_attr       = &gpio_dev_attr,
 -      .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+  ++};
+  ++
 -   /* gpio3 */
 -   static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
 -      { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
++ ++/* l4_per -> mcbsp2 */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
++ ++   .master         = &omap3xxx_l4_per_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp2_hwmod,
++ ++   .clk            = "mcbsp2_ick",
++ ++   .addr           = omap3xxx_mcbsp2_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
+  ++};
+  ++
 -   static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 -      { .role = "dbclk", .clk = "gpio3_dbck", },
++ ++/* mcbsp2 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
++ ++   &omap3xxx_l4_per__mcbsp2,
+  ++};
+  ++
 -   static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
 -      &omap3xxx_l4_per__gpio3,
++ ++static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
++ ++   .sidetone       = "mcbsp2_sidetone",
+  ++};
+  ++
 -   static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 -      .name           = "gpio3",
 -      .mpu_irqs       = omap3xxx_gpio3_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
 -      .main_clk       = "gpio3_ick",
 -      .opt_clks       = gpio3_opt_clks,
 -      .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
++ ++static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
++ ++   .name           = "mcbsp2",
++ ++   .class          = &omap3xxx_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp2_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
++ ++   .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
++ ++   .main_clk       = "mcbsp2_fck",
+  ++   .prcm           = {
+  ++           .omap2 = {
+  ++                   .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_GPIO3_SHIFT,
++ ++                   .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+  ++                   .module_offs = OMAP3430_PER_MOD,
+  ++                   .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+  ++           },
+  ++   },
 -      .slaves         = omap3xxx_gpio3_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
 -      .class          = &omap3xxx_gpio_hwmod_class,
 -      .dev_attr       = &gpio_dev_attr,
++ ++   .slaves         = omap3xxx_mcbsp2_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
++ ++   .dev_attr       = &omap34xx_mcbsp2_dev_attr,
+  ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+  ++};
+  ++
 -   /* gpio4 */
 -   static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
 -      { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
++ ++/* mcbsp3 */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
++ ++   { .name = "irq", .irq = 22 },
++ ++   { .name = "tx", .irq = 89 },
++ ++   { .name = "rx", .irq = 90 },
+  ++};
+  ++
 -   static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 -      { .role = "dbclk", .clk = "gpio4_dbck", },
++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 18 },
++ ++   { .name = "tx", .dma_req = 17 },
+  ++};
+  ++
 -   static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
 -      &omap3xxx_l4_per__gpio4,
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x49024000,
++ ++           .pa_end         = 0x490240ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
+  ++};
+  ++
 -   static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 -      .name           = "gpio4",
 -      .mpu_irqs       = omap3xxx_gpio4_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
 -      .main_clk       = "gpio4_ick",
 -      .opt_clks       = gpio4_opt_clks,
 -      .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
++ ++/* l4_per -> mcbsp3 */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
++ ++   .master         = &omap3xxx_l4_per_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp3_hwmod,
++ ++   .clk            = "mcbsp3_ick",
++ ++   .addr           = omap3xxx_mcbsp3_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp3 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
++ ++   &omap3xxx_l4_per__mcbsp3,
++ ++};
++ ++
++ ++static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
++ ++   .sidetone       = "mcbsp3_sidetone",
++ ++};
++ ++
++ ++static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
++ ++   .name           = "mcbsp3",
++ ++   .class          = &omap3xxx_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp3_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
++ ++   .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
++ ++   .main_clk       = "mcbsp3_fck",
+  ++   .prcm           = {
+  ++           .omap2 = {
+  ++                   .prcm_reg_id = 1,
 -                      .module_bit = OMAP3430_EN_GPIO4_SHIFT,
++ ++                   .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+  ++                   .module_offs = OMAP3430_PER_MOD,
+  ++                   .idlest_reg_id = 1,
 -                      .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+  ++           },
+  ++   },
 -      .slaves         = omap3xxx_gpio4_slaves,
 -      .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
 -      .class          = &omap3xxx_gpio_hwmod_class,
 -      .dev_attr       = &gpio_dev_attr,
++ ++   .slaves         = omap3xxx_mcbsp3_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
++ ++   .dev_attr       = &omap34xx_mcbsp3_dev_attr,
+  ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+  ++};
+  ++
 -   /* gpio5 */
 -   static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 -      { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
++ ++/* mcbsp4 */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
++ ++   { .name = "irq", .irq = 23 },
++ ++   { .name = "tx", .irq = 54 },
++ ++   { .name = "rx", .irq = 55 },
+  ++};
+  ++
 -   static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 -      { .role = "dbclk", .clk = "gpio5_dbck", },
++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 20 },
++ ++   { .name = "tx", .dma_req = 19 },
+  ++};
+  ++
 -   static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
 -      &omap3xxx_l4_per__gpio5,
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x49026000,
++ ++           .pa_end         = 0x490260ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
+   +};
+   +
 -   static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 -      .name           = "gpio5",
 -      .mpu_irqs       = omap3xxx_gpio5_irqs,
 -      .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
 -      .main_clk       = "gpio5_ick",
 -      .opt_clks       = gpio5_opt_clks,
 -      .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
   - static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
   -    { .role = "dbclk", .clk = "gpio5_dbck", },
++ ++/* l4_per -> mcbsp4 */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
++ ++   .master         = &omap3xxx_l4_per_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp4_hwmod,
++ ++   .clk            = "mcbsp4_ick",
++ ++   .addr           = omap3xxx_mcbsp4_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++  +};
++  +
   - static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
   -    &omap3xxx_l4_per__gpio5,
++ ++/* mcbsp4 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
++ ++   &omap3xxx_l4_per__mcbsp4,
++  +};
++  +
   - static struct omap_hwmod omap3xxx_gpio5_hwmod = {
   -    .name           = "gpio5",
   -    .mpu_irqs       = omap3xxx_gpio5_irqs,
   -    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
   -    .main_clk       = "gpio5_ick",
   -    .opt_clks       = gpio5_opt_clks,
   -    .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
++ ++static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
++ ++   .name           = "mcbsp4",
++ ++   .class          = &omap3xxx_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp4_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
++ ++   .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
++ ++   .main_clk       = "mcbsp4_fck",
+   +   .prcm           = {
+   +           .omap2 = {
+   +                   .prcm_reg_id = 1,
 - -                    .module_bit = OMAP3430_EN_GPIO5_SHIFT,
++ ++                   .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
+   +                   .module_offs = OMAP3430_PER_MOD,
+   +                   .idlest_reg_id = 1,
 - -                    .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
+   +           },
+   +   },
 - -    .slaves         = omap3xxx_gpio5_slaves,
 - -    .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
 - -    .class          = &omap3xxx_gpio_hwmod_class,
 - -    .dev_attr       = &gpio_dev_attr,
++ ++   .slaves         = omap3xxx_mcbsp4_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
+   +   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+   +};
+   +
 - - /* gpio6 */
 - - static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
 - -    { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
++ ++/* mcbsp5 */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
++ ++   { .name = "irq", .irq = 27 },
++ ++   { .name = "tx", .irq = 81 },
++ ++   { .name = "rx", .irq = 82 },
+   +};
+   +
 - - static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 - -    { .role = "dbclk", .clk = "gpio6_dbck", },
++ ++static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
++ ++   { .name = "rx", .dma_req = 22 },
++ ++   { .name = "tx", .dma_req = 21 },
+   +};
+   +
 - - static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
 - -    &omap3xxx_l4_per__gpio6,
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
++ ++   {
++ ++           .name           = "mpu",
++ ++           .pa_start       = 0x48096000,
++ ++           .pa_end         = 0x480960ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
+   +};
+   +
 - - static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 - -    .name           = "gpio6",
 - -    .mpu_irqs       = omap3xxx_gpio6_irqs,
 - -    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
 - -    .main_clk       = "gpio6_ick",
 - -    .opt_clks       = gpio6_opt_clks,
 - -    .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
++ ++/* l4_core -> mcbsp5 */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
++ ++   .master         = &omap3xxx_l4_core_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp5_hwmod,
++ ++   .clk            = "mcbsp5_ick",
++ ++   .addr           = omap3xxx_mcbsp5_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
++ ++   .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++};
++ ++
++ ++/* mcbsp5 slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
++ ++   &omap3xxx_l4_core__mcbsp5,
++ ++};
++ ++
++ ++static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
++ ++   .name           = "mcbsp5",
++ ++   .class          = &omap3xxx_mcbsp_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp5_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
++ ++   .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
++ ++   .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
++ ++   .main_clk       = "mcbsp5_fck",
+   +   .prcm           = {
+   +           .omap2 = {
+   +                   .prcm_reg_id = 1,
 - -                    .module_bit = OMAP3430_EN_GPIO6_SHIFT,
 - -                    .module_offs = OMAP3430_PER_MOD,
++ ++                   .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
++ ++                   .module_offs = CORE_MOD,
+   +                   .idlest_reg_id = 1,
 - -                    .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
+   +           },
+   +   },
 - -    .slaves         = omap3xxx_gpio6_slaves,
 - -    .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
 - -    .class          = &omap3xxx_gpio_hwmod_class,
 - -    .dev_attr       = &gpio_dev_attr,
++ ++   .slaves         = omap3xxx_mcbsp5_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
+   +   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+   +};
++ ++/* 'mcbsp sidetone' class */
+   +
 - - /* dma_system -> L3 */
 - - static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
 - -    .master         = &omap3xxx_dma_system_hwmod,
 - -    .slave          = &omap3xxx_l3_main_hwmod,
 - -    .clk            = "core_l3_ick",
 - -    .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
++ ++   .sysc_offs      = 0x0010,
++ ++   .sysc_flags     = SYSC_HAS_AUTOIDLE,
++ ++   .sysc_fields    = &omap_hwmod_sysc_type1,
+   +};
+   +
 - - /* dma attributes */
 - - static struct omap_dma_dev_attr dma_dev_attr = {
 - -    .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 - -                            IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 - -    .lch_count = 32,
++ ++static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
++ ++   .name = "mcbsp_sidetone",
++ ++   .sysc = &omap3xxx_mcbsp_sidetone_sysc,
+   +};
+   +
 - - static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 - -    .rev_offs       = 0x0000,
 - -    .sysc_offs      = 0x002c,
 - -    .syss_offs      = 0x0028,
 - -    .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 - -                       SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 - -                       SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 - -    .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 - -                       MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 - -    .sysc_fields    = &omap_hwmod_sysc_type1,
++ ++/* mcbsp2_sidetone */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
++ ++   { .name = "irq", .irq = 4 },
+   +};
+   +
 - - static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 - -    .name = "dma",
 - -    .sysc = &omap3xxx_dma_sysc,
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
++ ++   {
++ ++           .name           = "sidetone",
++ ++           .pa_start       = 0x49028000,
++ ++           .pa_end         = 0x490280ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
+   +};
+   +
 - - /* dma_system */
 - - static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
 - -    { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
 - -    { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
 - -    { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
 - -    { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
++ ++/* l4_per -> mcbsp2_sidetone */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
++ ++   .master         = &omap3xxx_l4_per_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
++ ++   .clk            = "mcbsp2_ick",
++ ++   .addr           = omap3xxx_mcbsp2_sidetone_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
++ ++   .user           = OCP_USER_MPU,
+   +};
+   +
 - - static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
 - -    {
 - -            .pa_start       = 0x48056000,
 - -            .pa_end         = 0x4a0560ff,
 - -            .flags          = ADDR_TYPE_RT
++ ++/* mcbsp2_sidetone slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
++ ++   &omap3xxx_l4_per__mcbsp2_sidetone,
++ ++};
++ ++
++ ++static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
++ ++   .name           = "mcbsp2_sidetone",
++ ++   .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
++ ++   .main_clk       = "mcbsp2_fck",
++ ++   .prcm           = {
++ ++           .omap2 = {
++ ++                   .prcm_reg_id = 1,
++ ++                    .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
++ ++                   .module_offs = OMAP3430_PER_MOD,
++ ++                   .idlest_reg_id = 1,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
++ ++           },
+   +   },
++ ++   .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
++ ++   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+   +};
+   +
 - - /* dma_system master ports */
 - - static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
 - -    &omap3xxx_dma_system__l3,
++ ++/* mcbsp3_sidetone */
++ ++static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
++ ++   { .name = "irq", .irq = 5 },
+   +};
+   +
 - - /* l4_cfg -> dma_system */
 - - static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
 - -    .master         = &omap3xxx_l4_core_hwmod,
 - -    .slave          = &omap3xxx_dma_system_hwmod,
 - -    .clk            = "core_l4_ick",
 - -    .addr           = omap3xxx_dma_system_addrs,
 - -    .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
 - -    .user           = OCP_USER_MPU | OCP_USER_SDMA,
++ ++static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
++ ++   {
++ ++           .name           = "sidetone",
++ ++           .pa_start       = 0x4902A000,
++ ++           .pa_end         = 0x4902A0ff,
++ ++           .flags          = ADDR_TYPE_RT
++ ++   },
+   +};
+   +
 - - /* dma_system slave ports */
 - - static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
 - -    &omap3xxx_l4_core__dma_system,
++ ++/* l4_per -> mcbsp3_sidetone */
++ ++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
++ ++   .master         = &omap3xxx_l4_per_hwmod,
++ ++   .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
++ ++   .clk            = "mcbsp3_ick",
++ ++   .addr           = omap3xxx_mcbsp3_sidetone_addrs,
++ ++   .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
++ ++   .user           = OCP_USER_MPU,
+   +};
+   +
 - - static struct omap_hwmod omap3xxx_dma_system_hwmod = {
 - -    .name           = "dma",
 - -    .class          = &omap3xxx_dma_hwmod_class,
 - -    .mpu_irqs       = omap3xxx_dma_system_irqs,
 - -    .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
 - -    .main_clk       = "core_l3_ick",
 - -    .prcm = {
++ ++/* mcbsp3_sidetone slave ports */
++ ++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
++ ++   &omap3xxx_l4_per__mcbsp3_sidetone,
++ ++};
++ ++
++ ++static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
++ ++   .name           = "mcbsp3_sidetone",
++ ++   .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
++ ++   .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
++ ++   .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
++ ++   .main_clk       = "mcbsp3_fck",
++ ++   .prcm           = {
+   +           .omap2 = {
 - -                    .module_offs            = CORE_MOD,
 - -                    .prcm_reg_id            = 1,
 - -                    .module_bit             = OMAP3430_ST_SDMA_SHIFT,
 - -                    .idlest_reg_id          = 1,
 - -                    .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
++ ++                   .prcm_reg_id = 1,
++ ++                   .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
++ ++                   .module_offs = OMAP3430_PER_MOD,
++ ++                   .idlest_reg_id = 1,
++ ++                   .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+   +           },
+   +   },
 - -    .slaves         = omap3xxx_dma_system_slaves,
 - -    .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
 - -    .masters        = omap3xxx_dma_system_masters,
 - -    .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
 - -    .dev_attr       = &dma_dev_attr,
++ ++   .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
++ ++   .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
+   +   .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 - -    .flags          = HWMOD_NO_IDLEST,
+   +};
+   +
++ ++
     /* SR common */
     static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
        .clkact_shift   = 20,
@@@@@@ -2852,22 -2285,8 -2725,8 -2217,8 -3064,25 +3572,25 @@@@@@ static __initdata struct omap_hwmod *om
        &omap3xxx_l4_core_hwmod,
        &omap3xxx_l4_per_hwmod,
        &omap3xxx_l4_wkup_hwmod,
++++    &omap3xxx_mmc1_hwmod,
++++    &omap3xxx_mmc2_hwmod,
++++    &omap3xxx_mmc3_hwmod,
        &omap3xxx_mpu_hwmod,
        &omap3xxx_iva_hwmod,
 +++ 
 +++    &omap3xxx_timer1_hwmod,
 +++    &omap3xxx_timer2_hwmod,
 +++    &omap3xxx_timer3_hwmod,
 +++    &omap3xxx_timer4_hwmod,
 +++    &omap3xxx_timer5_hwmod,
 +++    &omap3xxx_timer6_hwmod,
 +++    &omap3xxx_timer7_hwmod,
 +++    &omap3xxx_timer8_hwmod,
 +++    &omap3xxx_timer9_hwmod,
 +++    &omap3xxx_timer10_hwmod,
 +++    &omap3xxx_timer11_hwmod,
 +++    &omap3xxx_timer12_hwmod,
 +++ 
        &omap3xxx_wd_timer2_hwmod,
        &omap3xxx_uart1_hwmod,
        &omap3xxx_uart2_hwmod,
@@@@@@ -2902,6 -2321,9 -2761,18 -2253,6 -3117,6 +3625,18 @@@@@@
        /* dma_system class*/
        &omap3xxx_dma_system_hwmod,
     
++ ++   /* mcbsp class */
++ ++   &omap3xxx_mcbsp1_hwmod,
++ ++   &omap3xxx_mcbsp2_hwmod,
++ ++   &omap3xxx_mcbsp3_hwmod,
++ ++   &omap3xxx_mcbsp4_hwmod,
++ ++   &omap3xxx_mcbsp5_hwmod,
++ ++   &omap3xxx_mcbsp2_sidetone_hwmod,
++ ++   &omap3xxx_mcbsp3_sidetone_hwmod,
++ ++
+  ++   /* mailbox class */
+  ++   &omap3xxx_mailbox_hwmod,
+  ++
        /* mcspi class */
        &omap34xx_mcspi1,
        &omap34xx_mcspi2,

diff --cc arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 2c5882792e0150068ff1d4d36a1b67abff1a464f,79a8601789138faee5c7414be7e8fe30cebdf633,673b011403cb2e4181b9266fc334db84e0fc0d76,79a8601789138faee5c7414be7e8fe30cebdf633,9398c2db7258747c4d1c2dc5cbfd1c11bc363c42..7dbcdf751c02562561858c2c8d136b536a1b6c2c
--- 1/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
--- 3/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
--- 4/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
--- 5/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@@@@@ -25,6 -25,6 -25,7 -25,6 -25,7 +25,8 @@@@@@
     #include <plat/gpio.h>
     #include <plat/dma.h>
     #include <plat/mcspi.h>
++ ++#include <plat/mcbsp.h>
++++ #include <plat/mmc.h>
     
     #include "omap_hwmod_common_data.h"
     

diff --cc arch/arm/mach-omap2/prcm-common.h
Simple merge

diff --cc arch/arm/plat-omap/include/plat/omap_hwmod.h
Simple merge