arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk

We need set-rate-parent flags for the display's clock path so that the
DSS driver can change the clock rate of the PLL.

This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock
node, which is only a gate clock, allowing the setting of the clock rate
to propagate to the PLL.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
Acked-by: Tero Kristo <t-kristo@ti.com>

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 470f39c4e326ab135ea4435f7e0fbb64b201b991..357bedeebfac45e451a57ca736cf993bd2698c24 100644 (file)
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1531,6 +1531,7 @@
                clocks = <&dpll_per_h12x2_ck>;
                ti,bit-shift = <8>;
                reg = <0x1120>;
+               ti,set-rate-parent;
        };
 
        dss_hdmi_clk: dss_hdmi_clk {