#define APCI3120_EOS_MODE 2
#define APCI3120_DMA_MODE 3
-#define APCI3120_RD_STATUS 0x02
#define APCI3120_RD_FIFO 0x00
/* status register bits */
#define APCI3120_TIMER_DISABLE 0
#define APCI3120_TIMER_ENABLE 1
-#define APCI3120_RD_STATUS 0x02
#define APCI3120_FC_TIMER 0x1000
#define APCI3120_COUNTER 3
{
unsigned int status;
- status = inw(dev->iobase + APCI3120_RD_STATUS);
+ status = inw(dev->iobase + APCI3120_STATUS_REG);
if ((status & APCI3120_EOC) == 0)
return 0;
return -EBUSY;
outw(devpriv->ctrl, dev->iobase + APCI3120_CTRL_REG);
apci3120_ai_reset_fifo(dev);
- inw(dev->iobase + APCI3120_RD_STATUS); /* flush A/D status register */
+ inw(dev->iobase + APCI3120_STATUS_REG);
return 0;
}
outb(devpriv->mode, dev->iobase + APCI3120_MODE_REG);
apci3120_ai_reset_fifo(dev);
- inw(dev->iobase + APCI3120_RD_STATUS);
+ inw(dev->iobase + APCI3120_STATUS_REG);
devpriv->ui_DmaActualBuffer = 0;
devpriv->ai_running = 0;
unsigned short int_daq;
unsigned int int_amcc;
- int_daq = inw(dev->iobase + APCI3120_RD_STATUS) & 0xf000; /* get IRQ reasons */
+ int_daq = inw(dev->iobase + APCI3120_STATUS_REG) & 0xf000;
int_amcc = inl(devpriv->amcc + AMCC_OP_REG_INTCSR);
if ((!int_daq) && (!(int_amcc & ANY_S593X_INT))) {
if (devpriv->b_Timer2Mode == APCI3120_TIMER) {
data[0] = apci3120_timer_read(dev, 2);
} else { /* Read watch dog status */
-
- us_StatusValue = inw(dev->iobase + APCI3120_RD_STATUS);
+ us_StatusValue = inw(dev->iobase + APCI3120_STATUS_REG);
us_StatusValue =
((us_StatusValue & APCI3120_FC_TIMER) >> 12) & 1;
if (us_StatusValue == 1)
unsigned int val;
/* the input channels are bits 11:8 of the status reg */
- val = inw(dev->iobase + APCI3120_RD_STATUS);
+ val = inw(dev->iobase + APCI3120_STATUS_REG);
data[1] = (val >> 8) & 0xf;
return insn->n;
{
unsigned int status;
- status = inw(dev->iobase + APCI3120_RD_STATUS);
+ status = inw(dev->iobase + APCI3120_STATUS_REG);
if (status & 0x0001) /* waiting for DA_READY */
return 0;
return -EBUSY;
#define APCI3120_CTRL_GATE(x) (1 << (12 + (x)))
#define APCI3120_CTRL_PR(x) (((x) & 0xf) << 8)
#define APCI3120_CTRL_PA(x) (((x) & 0xf) << 0)
+#define APCI3120_STATUS_REG 0x02
#define APCI3120_STATUS_TO_VERSION(x) (((x) >> 4) & 0xf)
#define APCI3120_TIMER_REG 0x04
#define APCI3120_CHANLIST_REG 0x06
}
}
- status = inw(dev->iobase + APCI3120_RD_STATUS);
+ status = inw(dev->iobase + APCI3120_STATUS_REG);
if (APCI3120_STATUS_TO_VERSION(status) == APCI3120_REVB ||
context == BOARD_APCI3001)
devpriv->osc_base = APCI3120_REVB_OSC_BASE;