drm/i915: Distinguish between timeout and error in sideband transactions
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 23 Feb 2017 14:10:20 +0000 (14:10 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 27 Feb 2017 17:22:19 +0000 (17:22 +0000)
After initiating a sideband transaction, we only want to wait for the
transaction to become idle. If, as we are, we wait for both the busy
and error flag to clear, if an error is raised we just spin until the
timeout. Once the hw is idle, we can then check to see if the hw flagged
an error, and report it distinctly.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170223141020.13250-1-chris@chris-wilson.co.uk
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_sideband.c

index 9f782b5eb6e612bf13337f2e1530cb29993d2739..7d971cb5611683bc8a7927e6497b4da402bfb176 100644 (file)
@@ -216,6 +216,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
        }
 
        I915_WRITE(SBI_ADDR, (reg << 16));
+       I915_WRITE(SBI_DATA, 0);
 
        if (destination == SBI_ICLK)
                value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
@@ -225,10 +226,15 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
 
        if (intel_wait_for_register(dev_priv,
                                    SBI_CTL_STAT,
-                                   SBI_BUSY | SBI_RESPONSE_FAIL,
+                                   SBI_BUSY,
                                    0,
                                    100)) {
-               DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
+               DRM_ERROR("timeout waiting for SBI to complete read\n");
+               return 0;
+       }
+
+       if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
+               DRM_ERROR("error during SBI read of reg %x\n", reg);
                return 0;
        }
 
@@ -260,10 +266,16 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 
        if (intel_wait_for_register(dev_priv,
                                    SBI_CTL_STAT,
-                                   SBI_BUSY | SBI_RESPONSE_FAIL,
+                                   SBI_BUSY,
                                    0,
                                    100)) {
-               DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
+               DRM_ERROR("timeout waiting for SBI to complete write\n");
+               return;
+       }
+
+       if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
+               DRM_ERROR("error during SBI write of %x to reg %x\n",
+                         value, reg);
                return;
        }
 }