drm/i915: Reinit display irqs and hpd from chv pipe-a power well

On chv the pipe-a power well is the new disp2d well, and it kills pretty
much everything in the display block. So we need to do the the same
dance that vlv does wrt. display irqs and hpd when the power well goes
up or down.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index dcbecffc6b5f388cb541af18a04e8cbe5468bb17..f5a78d53e2978ed1c4f25cdaa73d9fcb0ca887bb 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -577,6 +577,23 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
                     power_well->data != PIPE_C);
 
        chv_set_pipe_power_well(dev_priv, power_well, true);
+
+       if (power_well->data == PIPE_A) {
+               spin_lock_irq(&dev_priv->irq_lock);
+               valleyview_enable_display_irqs(dev_priv);
+               spin_unlock_irq(&dev_priv->irq_lock);
+
+               /*
+                * During driver initialization/resume we can avoid restoring the
+                * part of the HW/SW state that will be inited anyway explicitly.
+                */
+               if (dev_priv->power_domains.initializing)
+                       return;
+
+               intel_hpd_init(dev_priv);
+
+               i915_redisable_vga_power_on(dev_priv->dev);
+       }
 }
 
 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
@@ -586,6 +603,12 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
                     power_well->data != PIPE_B &&
                     power_well->data != PIPE_C);
 
+       if (power_well->data == PIPE_A) {
+               spin_lock_irq(&dev_priv->irq_lock);
+               valleyview_disable_display_irqs(dev_priv);
+               spin_unlock_irq(&dev_priv->irq_lock);
+       }
+
        chv_set_pipe_power_well(dev_priv, power_well, false);
 
        if (power_well->data == PIPE_A)