ath9k: Fix PLL powersave for AR9485

Use the value in ah->config.pll_pwrsave to determine
which array needs to be loaded. Also, initialize
pll_pwrsave to 1 by default.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 4335ccbe7d7e078537216301a4fdb2120d3ee7fb..ea33f8dcc171ff80c9851fd3fe38cfc643982d0e 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -195,16 +195,16 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
                INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
                               ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 
-               if (ah->config.no_pll_pwrsave) {
+               if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
+                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
                        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
+                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
                } else {
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
+                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
                        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
+                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
                }
        } else if (AR_SREV_9462_21(ah)) {
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 2bb3b334a23f22f083ed633caf177b6a3799622d..e124ee240dc86fc6f5ecc91c26621364c80011ce 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -341,7 +341,7 @@ struct ath9k_ops_config {
        u32 ant_ctrl_comm2g_switch_enable;
        bool xatten_margin_cfg;
        bool alt_mingainidx;
-       bool no_pll_pwrsave;
+       bool pll_pwrsave;
        bool tx_gain_buffalo;
        bool led_active_high;
 };

diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 6c6e88495394e1897edb4db3768bd6de8aee24e7..ca66fab78fba1338033f9bc061a0fc1d520e63bd 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -437,8 +437,14 @@ static void ath9k_init_pcoem_platform(struct ath_softc *sc)
                ath_info(common, "Enable WAR for ASPM D3/L1\n");
        }
 
+       /*
+        * The default value of pll_pwrsave is 1.
+        * For certain AR9485 cards, it is set to 0.
+        */
+       ah->config.pll_pwrsave = 1;
+
        if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
-               ah->config.no_pll_pwrsave = true;
+               ah->config.pll_pwrsave = 0;
                ath_info(common, "Disable PLL PowerSave\n");
        }