drm/nv50: fix suspend/resume with DP outputs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 9f28b94e479bd1c7e7ba1f68bb59f29975559dbf..e1df8209cd0f58424c41fea37c4758801e1f4aad 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -48,6 +48,8 @@ struct nouveau_encoder {
        union {
                struct {
                        int mc_unknown;
+                       uint32_t unk0;
+                       uint32_t unk1;
                        int dpcd_version;
                        int link_nr;
                        int link_bw;

diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index aa9b310e41be0c7d2a26d33a598879fa98e77ba6..6ca80a3fe70db02084ed9730fe857b92345dd16f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -826,6 +826,7 @@
 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2                          0x02000000
 #define NV50_SOR_DP_UNK118(i,l)          (0x0061c118 + (i) * 0x800 + (l) * 0x80)
 #define NV50_SOR_DP_UNK120(i,l)          (0x0061c120 + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_UNK128(i,l)          (0x0061c128 + (i) * 0x800 + (l) * 0x80)
 #define NV50_SOR_DP_UNK130(i,l)          (0x0061c130 + (i) * 0x800 + (l) * 0x80)
 
 #define NV50_PDISPLAY_USER(i)                        ((i) * 0x1000 + 0x00640000)

diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 34156b69594f73250f0cf4dc3ac26d489ddb367d..580a5d10be9322cb581fc357a3b5215e7a3fcf10 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -783,6 +783,37 @@ ack:
        nv_wr32(dev, 0x610030, 0x80000000);
 }
 
+static void
+nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
+{
+       int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
+       struct drm_encoder *encoder;
+       uint32_t tmp, unk0 = 0, unk1 = 0;
+
+       if (dcb->type != OUTPUT_DP)
+               return;
+
+       list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+               struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+
+               if (nv_encoder->dcb == dcb) {
+                       unk0 = nv_encoder->dp.unk0;
+                       unk1 = nv_encoder->dp.unk1;
+                       break;
+               }
+       }
+
+       if (unk0 || unk1) {
+               tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
+               tmp &= 0xfffffe03;
+               nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
+
+               tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
+               tmp &= 0xfef080c0;
+               nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
+       }
+}
+
 static void
 nv50_display_unk20_handler(struct drm_device *dev)
 {
@@ -806,6 +837,8 @@ nv50_display_unk20_handler(struct drm_device *dev)
 
        nouveau_bios_run_display_table(dev, dcbent, script, pclk);
 
+       nv50_display_unk20_dp_hack(dev, dcbent);
+
        tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
        tmp &= ~0x000000f;
        nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);

diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index 0c68698f23df7d94b86e0a0a6ceb1a45c7b9bdae..b11eaf9c5c7cd0575eec63e20d7217b7c8fd49c1 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -321,18 +321,23 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
        encoder->possible_clones = 0;
 
        if (nv_encoder->dcb->type == OUTPUT_DP) {
-               uint32_t mc, or = nv_encoder->or;
+               int or = nv_encoder->or, link = !(entry->dpconf.sor.link & 1);
+               uint32_t tmp;
 
                if (dev_priv->chipset < 0x90 ||
                    dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
-                       mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
+                       tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
                else
-                       mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
+                       tmp = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
 
-               switch ((mc & 0x00000f00) >> 8) {
+               switch ((tmp & 0x00000f00) >> 8) {
                case 8:
                case 9:
-                       nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16;
+                       nv_encoder->dp.mc_unknown = (tmp & 0x000f0000) >> 16;
+                       tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
+                       nv_encoder->dp.unk0 = tmp & 0x000001fc;
+                       tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
+                       nv_encoder->dp.unk1 = tmp & 0x010f7f3f;
                        break;
                default:
                        break;