[PATCH] ARM: 2797/1: OMAP update 1/11: Update include files
authorTony Lindgren <tony@atomide.com>
Sun, 10 Jul 2005 18:58:06 +0000 (19:58 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Sun, 10 Jul 2005 18:58:06 +0000 (19:58 +0100)
Patch from Tony Lindgren

This patch by various OMAP developers syncs the OMAP
specific include files with the linux-omap tree.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
include/asm-arm/arch-omap/board-h2.h
include/asm-arm/arch-omap/board-h3.h
include/asm-arm/arch-omap/board-osk.h
include/asm-arm/arch-omap/board.h
include/asm-arm/arch-omap/hardware.h
include/asm-arm/arch-omap/irqs.h
include/asm-arm/arch-omap/omap16xx.h
include/asm-arm/arch-omap/system.h

index 60f002b72983277d226630c9febf6baaae6efdc3..39ca5a31aeea7144982c9c2658daa8bd154d72be 100644 (file)
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START            0x04000300
 
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE             SZ_32M
-#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
-
 /* Samsung NAND flash at CS2B or CS3(NAND Boot) */
 #define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
 #define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
index e4d1cd231731af086a9819cbba44b890ce0c1d47..1b12c1dcc2faf54c30a0b2b211ce999e0fa3a2b2 100644 (file)
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START            0x04000300
 
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE             SZ_32M
-#define OMAP_NOR_FLASH_START1          0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2          0x0A000000 /* CS2B */
-
 /* Samsung NAND flash at CS2B or CS3(NAND Boot) */
 #define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
 #define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
index aaa49a0fbd218c7c11e89c88669cd411270c190a..2b1a8a4fe44ed21b9a69a3d65ecc7bbe29ff0b4a 100644 (file)
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
 #define OMAP_OSK_ETHR_START            0x04800300
 
-/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
-#define OMAP_OSK_NOR_FLASH_BASE                0xD8000000
-#define OMAP_OSK_NOR_FLASH_SIZE                SZ_32M
-#define OMAP_OSK_NOR_FLASH_START       0x00000000
-
 #endif /*  __ASM_ARCH_OMAP_OSK_H */
 
index 1cefd60b6f2a0aa6eacb2a7ce37ebc2b43fac33a..95bd625480c13afd715fe45a70e0a40bb9c57cf0 100644 (file)
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK         0x4f01
 #define OMAP_TAG_MMC           0x4f02
-#define OMAP_TAG_UART          0x4f03
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 #define OMAP_TAG_USB           0x4f04
 #define OMAP_TAG_LCD           0x4f05
 #define OMAP_TAG_GPIO_SWITCH   0x4f06
+#define OMAP_TAG_UART          0x4f07
 
 #define OMAP_TAG_BOOT_REASON    0x4f80
 #define OMAP_TAG_FLASH_PART    0x4f81
@@ -35,7 +36,7 @@ struct omap_mmc_config {
        s16 mmc1_switch_pin, mmc2_switch_pin;
 };
 
-struct omap_uart_config {
+struct omap_serial_console_config {
        u8 console_uart;
        u32 console_speed;
 };
@@ -82,7 +83,8 @@ struct omap_lcd_config {
  */
 #define OMAP_GPIO_SWITCH_TYPE_COVER            0x0000
 #define OMAP_GPIO_SWITCH_TYPE_CONNECTION       0x0001
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED         0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT           0x0002
 struct omap_gpio_switch_config {
        char name[12];
        u16 gpio;
@@ -99,6 +101,10 @@ struct omap_boot_reason_config {
        char reason_str[12];
 };
 
+struct omap_uart_config {
+       /* Bit field of UARTs present; bit 0 --> UART1 */
+       unsigned int enabled_uarts;
+};
 
 struct omap_board_config_entry {
        u16 tag;
index 37e06c782bdf029499cfe4a4a12d94c62b6c5d6e..48258c7f6541ca0c890b0df2e68b2739c6704bc2 100644 (file)
  * ---------------------------------------------------------------------------
  */
 
+/*
+ * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE   (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE   (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE   (0xfffec700)
+#define MPU_TIMER_FREE         (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
+#define MPU_TIMER_AR           (1 << 1)
+#define MPU_TIMER_ST           (1 << 0)
+
 /*
  * ----------------------------------------------------------------------------
  * Clocks
@@ -78,6 +91,7 @@
 
 /* DSP clock control */
 #define DSP_CONFIG_REG_BASE     (0xe1008000)
+#define DSP_CKCTL              (DSP_CONFIG_REG_BASE + 0x0)
 #define DSP_IDLECT1            (DSP_CONFIG_REG_BASE + 0x4)
 #define DSP_IDLECT2            (DSP_CONFIG_REG_BASE + 0x8)
 
  */
 #define ULPD_REG_BASE          (0xfffe0800)
 #define ULPD_IT_STATUS         (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3       (ULPD_REG_BASE + 0x24)
 #define ULPD_CLOCK_CTRL                (ULPD_REG_BASE + 0x30)
 #      define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
 #      define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
  * Processor specific defines
  * ---------------------------------------------------------------------------
  */
-#ifdef CONFIG_ARCH_OMAP730
-#include "omap730.h"
-#endif
 
-#ifdef CONFIG_ARCH_OMAP1510
+#include "omap730.h"
 #include "omap1510.h"
-#endif
-
-#ifdef CONFIG_ARCH_OMAP16XX
 #include "omap16xx.h"
-#endif
 
 /*
  * ---------------------------------------------------------------------------
index 6701fd9e5f9b9e3cf8dfd1297e3957f9329b9074..0d05a7c957d155799e1acaf61a4dab8cf7184f42 100644 (file)
 #define INT_1610_GPIO_BANK3    (41 + IH2_BASE)
 #define INT_1610_MMC2          (42 + IH2_BASE)
 #define INT_1610_CF            (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ   (46 + IH2_BASE)
 #define INT_1610_GPIO_BANK4    (48 + IH2_BASE)
 #define INT_1610_SPI           (49 + IH2_BASE)
 #define INT_1610_DMA_CH6       (53 + IH2_BASE)
 #define IH_MPUIO_BASE          (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
 #define IH_BOARD_BASE          (16 + IH_MPUIO_BASE)
 
+#define OMAP_IRQ_BIT(irq)      (1 << ((irq) % 32))
+
 #ifndef __ASSEMBLY__
 extern void omap_init_irq(void);
 #endif
index 88b1fe43ae9eb4a531150d2f1ffd3422c8f9fafb..38a9b95e6a336c7e12a3ebef89c629b37a22b6d9 100644 (file)
 #define OMAP16XX_PWL_ENABLE    (OMAP16XX_PWL_BASE + 0x00)
 #define OMAP16XX_PWL_CLK_ENABLE        (OMAP16XX_PWL_BASE + 0x04)
 
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* 32-bit Watchdog timer in OMAP 16XX */
+#define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)
+#define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)
+#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
+#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
+#define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)
+#define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)
+#define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)
+#define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)
+#define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)
+#define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)
+
+#define WCLR_PRE_SHIFT         5
+#define WCLR_PTV_SHIFT         2
+
+#define WWPS_W_PEND_WSPR       (1 << 4)
+#define WWPS_W_PEND_WTGR       (1 << 3)
+#define WWPS_W_PEND_WLDR       (1 << 2)
+#define WWPS_W_PEND_WCRR       (1 << 1)
+#define WWPS_W_PEND_WCLR       (1 << 0)
+
+#define WSPR_ENABLE_0          (0x0000bbbb)
+#define WSPR_ENABLE_1          (0x00004444)
+#define WSPR_DISABLE_0         (0x0000aaaa)
+#define WSPR_DISABLE_1         (0x00005555)
+
 #endif /*  __ASM_ARCH_OMAP16XX_H */
 
index 17a2c4825f074af6d9f075ad07013b4b143f1753..ff37bc27e6034281e7686007210554c54377d420 100644 (file)
@@ -5,7 +5,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 #include <linux/config.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
+#include <asm/mach-types.h>
 
 static inline void arch_idle(void)
 {
@@ -14,7 +16,24 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode)
 {
-       omap_writew(1, ARM_RSTCT1);
+
+#ifdef CONFIG_ARCH_OMAP16XX
+       /*
+        * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+        * "Global Software Reset Affects Traffic Controller Frequency".
+        */
+       if (cpu_is_omap5912()) {
+               omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
+                                DPLL_CTL);
+               omap_writew(0x8, ARM_RSTCT1);
+       }
+#endif
+#ifdef CONFIG_MACH_VOICEBLUE
+       if (machine_is_voiceblue())
+               voiceblue_reset();
+       else
+#endif
+               omap_writew(1, ARM_RSTCT1);
 }
 
 #endif