.rate = CONFIG_SH_PCLK_FREQ,
};
-static struct clk module_clk = {
- .name = "module_clk",
+static struct clk peripheral_clk = {
+ .name = "peripheral_clk",
.parent = &master_clk,
.flags = CLK_ENABLE_ON_INIT,
};
*/
static struct clk *onchip_clocks[] = {
&master_clk,
- &module_clk,
+ &peripheral_clk,
&bus_clk,
&cpu_clk,
};
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "CMT0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "CMT1",
.channel_offset = 0x08,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 0, /* disabled due to code generation issues */
};
.name = "MTU2_0",
.channel_offset = -0x80,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_1",
.channel_offset = -0x100,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "MTU2_2",
.channel_offset = 0x80,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "CMT0",
.channel_offset = 0x10,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
.name = "CMT1",
.channel_offset = 0x20,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt1_resources[] = {
.name = "CMT2",
.channel_offset = 0x30,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt2_resources[] = {
.name = "CMT3",
.channel_offset = 0x40,
.timer_bit = 3,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt3_resources[] = {
.name = "CMT4",
.channel_offset = 0x50,
.timer_bit = 4,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource cmt4_resources[] = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU6",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu6_resources[] = {
.name = "TMU7",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu7_resources[] = {
.name = "TMU8",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu8_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU6",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu6_resources[] = {
.name = "TMU7",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu7_resources[] = {
.name = "TMU8",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu8_resources[] = {
.name = "TMU9",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu9_resources[] = {
.name = "TMU10",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu10_resources[] = {
.name = "TMU11",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu11_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
.name = "TMU3",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu3_resources[] = {
.name = "TMU4",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu4_resources[] = {
.name = "TMU5",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu5_resources[] = {
.name = "TMU0",
.channel_offset = 0x04,
.timer_bit = 0,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clockevent_rating = 200,
};
.name = "TMU1",
.channel_offset = 0x10,
.timer_bit = 1,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
.clocksource_rating = 200,
};
.name = "TMU2",
.channel_offset = 0x1c,
.timer_bit = 2,
- .clk = "module_clk",
+ .clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
signed char cdf, cdfm;
int scgd, scgdm, scgds;
- mclk = clk_get(NULL, "module_clk");
+ mclk = clk_get(NULL, "peripheral_clk");
if (IS_ERR(mclk)) {
return PTR_ERR(mclk);
} else {
sci_port->port.uartclk = CONFIG_CPU_CLOCK;
#elif defined(CONFIG_HAVE_CLK)
sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
- sci_port->dclk = clk_get(&dev->dev, "module_clk");
+ sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
sci_port->enable = sci_clk_enable;
sci_port->disable = sci_clk_disable;
#else
outw(v, HD64461_GPADR);
}
- sh_dac_output(0, CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
+ sh_dac_output(0, CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
sh_dac_disable(CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
}
static void dac_audio_set_rate(void)
{
unsigned long interval;
- struct clk *clk;
+ struct clk *clk;
- clk = clk_get(NULL, "module_clk");
- interval = (clk_get_rate(clk) / 4) / rate;
- clk_put(clk);
+ clk = clk_get(NULL, "peripheral_clk");
+ interval = (clk_get_rate(clk) / 4) / rate;
+ clk_put(clk);
ctrl_outl(interval, TMU1_TCOR);
ctrl_outl(interval, TMU1_TCNT);
}