crypto: inside-secure - fix the ring wr_cache offset

The EIP197_HIA_xDR_CFG_WR_CACHE macro was defined to use an offset of
23, which is wrong as it's actually 25. Fix this.

Reported-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/inside-secure/safexcel.h b/drivers/crypto/inside-secure/safexcel.h
index c17fdd40b99fe78648662e81844bf0283f1fa26e..0328a9314b90949f4e891e134afaa6e80c2b6379 100644 (file)
--- a/drivers/crypto/inside-secure/safexcel.h
+++ b/drivers/crypto/inside-secure/safexcel.h
@@ -99,7 +99,7 @@
 #define EIP197_HIA_xDR_WR_RES_BUF              BIT(22)
 #define EIP197_HIA_xDR_WR_CTRL_BUG             BIT(23)
 #define EIP197_HIA_xDR_WR_OWN_BUF              BIT(24)
-#define EIP197_HIA_xDR_CFG_WR_CACHE(n)         (((n) & 0x7) << 23)
+#define EIP197_HIA_xDR_CFG_WR_CACHE(n)         (((n) & 0x7) << 25)
 #define EIP197_HIA_xDR_CFG_RD_CACHE(n)         (((n) & 0x7) << 29)
 
 /* EIP197_HIA_CDR_THRESH */