if (speed > PIO_MAX_SPEED) {
outb(ICR_EFSFI, iobase + ICR);
w83977af_dma_receive(self);
- } else
+ } else {
outb(ICR_ERBRI, iobase + ICR);
+ }
/* Restore SSR */
outb(set, iobase + SSR);
w83977af_change_speed(self, speed);
dev_kfree_skb(skb);
return NETDEV_TX_OK;
- } else
- self->new_speed = speed;
+ }
+ self->new_speed = speed;
}
/* Save current set */
/* Clear bit, by writing 1 to it */
outb(AUDR_UNDR, iobase + AUDR);
- } else
+ } else {
self->netdev->stats.tx_packets++;
+ }
if (self->new_speed) {
w83977af_change_speed(self, self->new_speed);
} else {
/* Check if we have transferred all data to memory */
switch_bank(iobase, SET0);
- if (inb(iobase + USR) & USR_RDR) {
+ if (inb(iobase + USR) & USR_RDR)
udelay(80); /* Should be enough!? */
- }
skb = dev_alloc_skb(len + 1);
if (!skb) {
/* End of frame detected in FIFO */
if (isr & (ISR_FEND_I | ISR_FSF_I)) {
if (w83977af_dma_receive_complete(self)) {
-
/* Wait for next status FIFO interrupt */
new_icr |= ICR_EFSFI;
} else {
status = TRUE;
}
outb(set, iobase + SSR);
- } else
+ } else {
status = (self->rx_buff.state != OUTSIDE_FRAME);
+ }
return status;
}
if (self->io.speed > 115200) {
outb(ICR_EFSFI, iobase + ICR);
w83977af_dma_receive(self);
- } else
+ } else {
outb(ICR_ERBRI, iobase + ICR);
+ }
/* Restore bank register */
outb(set, iobase + SSR);