drm/i915: rename VLV IOSF sideband functions logically

Rename all VLV IOSF sideband register accessor functions to
vlv_<port>_{read,write}. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3a8409a31266ebf0f0544f4905621fa66420a439..bc0f6a55c74ba6cd30e05ad51111b082fbba5594 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1137,16 +1137,16 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
                u32 freq_sts, val;
 
                mutex_lock(&dev_priv->rps.hw_lock);
-               valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
+               vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
                                      &freq_sts);
                seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
                seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 
-               valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+               vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
                seq_printf(m, "max GPU freq: %d MHz\n",
                           vlv_gpu_freq(dev_priv->mem_freq, val));
 
-               valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+               vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
                seq_printf(m, "min GPU freq: %d MHz\n",
                           vlv_gpu_freq(dev_priv->mem_freq, val));
 
@@ -1787,27 +1787,27 @@ static int i915_dpio_info(struct seq_file *m, void *data)
        seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
 
        seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_DIV_A));
+                  vlv_dpio_read(dev_priv, _DPIO_DIV_A));
        seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_DIV_B));
+                  vlv_dpio_read(dev_priv, _DPIO_DIV_B));
 
        seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
+                  vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
        seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
+                  vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
 
        seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+                  vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
        seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+                  vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
 
        seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
+                  vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
        seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
-                  intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
+                  vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
 
        seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
-                  intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+                  vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
 
        mutex_unlock(&dev_priv->dpio_lock);
 

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a0dfca88668fd921fcadaf464e4d1677c426d88..28d14d6cf4cc872573b4756ef9d3d07f0c65eecb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1931,11 +1931,11 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
 
 /* intel_sideband.c */
-int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
-int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
-int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
-u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
-void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
+int vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+int vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
                   enum intel_sbi_destination destination);
 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index c0d7875b475c1a30b8893c9e76d1f03996de8cd1..588fa00e693880af520bd06df96be72a38fcdd64 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -214,7 +214,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
        mutex_lock(&dev_priv->rps.hw_lock);
        if (IS_VALLEYVIEW(dev_priv->dev)) {
                u32 freq;
-               valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq);
+               vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq);
                ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
        } else {
                ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e07ee4c73592f98f205cd2f11a886eb24debd770..2a9d0671f8c382b433f141588c1701a3dbf74951 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4245,24 +4245,24 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
         * PLLB opamp always calibrates to max value of 0x3f, force enable it
         * and set it to a reasonable value instead.
         */
-       reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
+       reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
        reg_val &= 0xffffff00;
        reg_val |= 0x00000030;
-       intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+       vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
 
-       reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
+       reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
        reg_val &= 0x8cffffff;
        reg_val = 0x8c000000;
-       intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+       vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
 
-       reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
+       reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
        reg_val &= 0xffffff00;
-       intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+       vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
 
-       reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
+       reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
        reg_val &= 0x00ffffff;
        reg_val |= 0xb0000000;
-       intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+       vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
 }
 
 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
@@ -4337,15 +4337,15 @@ static void vlv_update_pll(struct intel_crtc *crtc)
                vlv_pllb_recal_opamp(dev_priv);
 
        /* Set up Tx target for periodic Rcomp update */
-       intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
+       vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
 
        /* Disable target IRef on PLL */
-       reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
+       reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
        reg_val &= 0x00ffffff;
-       intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
+       vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
 
        /* Disable fast lock */
-       intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
+       vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
 
        /* Set idtafcrecal before PLL is enabled */
        mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
@@ -4359,47 +4359,47 @@ static void vlv_update_pll(struct intel_crtc *crtc)
         * Note: don't use the DAC post divider as it seems unstable.
         */
        mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
-       intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+       vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
 
        mdiv |= DPIO_ENABLE_CALIBRATION;
-       intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+       vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
 
        /* Set HBR and RBR LPF coefficients */
        if (adjusted_mode->clock == 162000 ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
-               intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+               vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
                                 0x005f0021);
        else
-               intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+               vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
                                 0x00d0000f);
 
        if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
                /* Use SSC source */
                if (!pipe)
-                       intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                       vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
                                         0x0df40000);
                else
-                       intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                       vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
                                         0x0df70000);
        } else { /* HDMI or VGA */
                /* Use bend source */
                if (!pipe)
-                       intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                       vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
                                         0x0df70000);
                else
-                       intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                       vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
                                         0x0df40000);
        }
 
-       coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
+       coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
        coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
        if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
            intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
                coreclk |= 0x01000000;
-       intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
+       vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
 
-       intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
+       vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
 
        for_each_encoder_on_crtc(dev, &crtc->base, encoder)
                if (encoder->pre_pll_enable)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 098e7c25f4effb7a7c585a03559c622c9eaeebf7..cdb1c2a6d2b28b5b057a0b2712d100816c230413 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1442,18 +1442,18 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder)
                int pipe = intel_crtc->pipe;
                u32 val;
 
-               val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
+               val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
                val = 0;
                if (pipe)
                        val |= (1<<21);
                else
                        val &= ~(1<<21);
                val |= 0x001000c4;
-               intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
+               vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
 
-               intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
+               vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
                                 0x00760018);
-               intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
+               vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
                                 0x00400888);
        }
 }
@@ -1469,19 +1469,19 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
                return;
 
        /* Program Tx lane resets to default */
-       intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
                         DPIO_PCS_TX_LANE2_RESET |
                         DPIO_PCS_TX_LANE1_RESET);
-       intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
                         DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
                         DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
                         (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
                                 DPIO_PCS_CLK_SOFT_RESET);
 
        /* Fix up inter-pair skew failure */
-       intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
-       intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
-       intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
+       vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
+       vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
+       vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
 }
 
 /*
@@ -1691,14 +1691,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
                return 0;
        }
 
-       intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
-       intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
-       intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
+       vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
+       vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
+       vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
                         uniqtranscale_reg_value);
-       intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
-       intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
-       intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
-       intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
+       vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
+       vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
+       vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
+       vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 83b63d72af837154e12728727581f614b1027664..8062a92e6e80cc57b1b08bd12575a08b487dad3a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1019,35 +1019,35 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
                return;
 
        /* Enable clock channels for this port */
-       val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
+       val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
        val = 0;
        if (pipe)
                val |= (1<<21);
        else
                val &= ~(1<<21);
        val |= 0x001000c4;
-       intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
+       vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
 
        /* HDMI 1.0V-2dB */
-       intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
-       intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
+       vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
+       vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
                         0x2b245f5f);
-       intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
+       vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
                         0x5578b83a);
-       intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
+       vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
                         0x0c782040);
-       intel_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
+       vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
                         0x2b247878);
-       intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
-       intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
+       vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
                         0x00002000);
-       intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
+       vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
                         DPIO_TX_OCALINIT_EN);
 
        /* Program lane clock */
-       intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
                         0x00760018);
-       intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
                         0x00400888);
 }
 
@@ -1062,23 +1062,23 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
                return;
 
        /* Program Tx lane resets to default */
-       intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
                         DPIO_PCS_TX_LANE2_RESET |
                         DPIO_PCS_TX_LANE1_RESET);
-       intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
                         DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
                         DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
                         (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
                         DPIO_PCS_CLK_SOFT_RESET);
 
        /* Fix up inter-pair skew failure */
-       intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
-       intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
-       intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
+       vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
+       vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
+       vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
 
-       intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
+       vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
                         0x00002000);
-       intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
+       vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
                         DPIO_TX_OCALINIT_EN);
 }
 
@@ -1090,8 +1090,8 @@ static void intel_hdmi_post_disable(struct intel_encoder *encoder)
 
        /* Reset lanes to avoid HDMI flicker (VLV w/a) */
        mutex_lock(&dev_priv->dpio_lock);
-       intel_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
-       intel_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
+       vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
+       vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
        mutex_unlock(&dev_priv->dpio_lock);
 }
 

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cd5bd88980bbc20876a02fec25969b88cadf9056..52f1b39148c0ab5684793772955449ff9b1ba25e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2566,10 +2566,10 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
        if (val == dev_priv->rps.cur_delay)
                return;
 
-       valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+       vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
 
        do {
-               valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+               vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
                if (time_after(jiffies, timeout)) {
                        DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
                        break;
@@ -2577,7 +2577,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
                udelay(10);
        } while (pval & 1);
 
-       valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+       vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
        if ((pval >> 8) != val)
                DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
                          val, pval >> 8);
@@ -2882,7 +2882,7 @@ int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
        u32 val, rp0;
 
-       valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
+       vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
 
        rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
        /* Clamp to max */
@@ -2895,9 +2895,9 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 {
        u32 val, rpe;
 
-       valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
+       vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
        rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
-       valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
+       vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
        rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
 
        return rpe;
@@ -2907,7 +2907,7 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
        u32 val;
 
-       valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+       vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
 
        return val & 0xff;
 }
@@ -3018,7 +3018,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
        I915_WRITE(GEN6_RC_CONTROL,
                   GEN7_RC_CTL_TO_MODE);
 
-       valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+       vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
        switch ((val >> 6) & 3) {
        case 0:
        case 1:

diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index a7c4b61e9c30aabd34d598e67a565cdb4e0dce6d..d150972da04865ae99e5319d94ac3188a13c806d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -63,7 +63,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
        return 0;
 }
 
-int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+int vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
 {
        int ret;
 
@@ -77,7 +77,7 @@ int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
        return ret;
 }
 
-int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+int vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
 {
        int ret;
 
@@ -91,7 +91,7 @@ int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
        return ret;
 }
 
-int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+int vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
 {
        int ret;
 
@@ -105,7 +105,7 @@ int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
        return ret;
 }
 
-u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
 {
        u32 val = 0;
 
@@ -115,7 +115,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
        return val;
 }
 
-void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
+void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 {
        vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
                        DPIO_OPCODE_REG_WRITE, reg, &val);