drm/amdgpu:add META_DATA struct for CSA/SRIOV v2

META-DATA is used in GFX cmd submit, we have two
format suit for META-DATA-init, one is legacy and another
is for chained-ib preempt, which is used in vulkan
UMD.

v2: drop use CP version number to judge if chain-ib
supports or not, we wait for it mature

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 59376fa69eba0d9e02b298ac0905a13ae000e8f7..675e12c425326e3a27b784059711a6267be99baa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -44,6 +44,7 @@ struct amdgpu_virt {
        uint32_t                        caps;
        struct amdgpu_bo                *csa_obj;
        uint64_t                        csa_vmid0_addr;
+       bool chained_ib_support;
        uint32_t                        reg_val_offs;
        struct mutex                    lock;
        struct amdgpu_irq_src           ack_irq;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 69543d4eef343aa7d80c178d5e957b4bb8235410..3c613c66d47d39f611dd8c3b140cf0d9fea328c4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -936,6 +936,13 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
                goto out;
        cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
        adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+
+       /* chain ib ucode isn't formal released, just disable it by far
+        * TODO: when ucod ready we should use ucode version to judge if
+        * chain-ib support or not.
+        */
+       adev->virt.chained_ib_support = false;
+
        adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 575d7aed5d32f2476f9056923b68bd768e66885e..719587b8b0cbe9da874f3a9db4a915f33d93cb65 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -28,4 +28,116 @@ void vi_srbm_select(struct amdgpu_device *adev,
                    u32 me, u32 pipe, u32 queue, u32 vmid);
 int vi_set_ip_blocks(struct amdgpu_device *adev);
 
+struct amdgpu_ce_ib_state
+{
+       uint32_t    ce_ib_completion_status;
+       uint32_t    ce_constegnine_count;
+       uint32_t    ce_ibOffset_ib1;
+       uint32_t    ce_ibOffset_ib2;
+}; /* Total of 4 DWORD */
+
+struct amdgpu_de_ib_state
+{
+       uint32_t    ib_completion_status;
+       uint32_t    de_constEngine_count;
+       uint32_t    ib_offset_ib1;
+       uint32_t    ib_offset_ib2;
+       uint32_t    preamble_begin_ib1;
+       uint32_t    preamble_begin_ib2;
+       uint32_t    preamble_end_ib1;
+       uint32_t    preamble_end_ib2;
+       uint32_t    draw_indirect_baseLo;
+       uint32_t    draw_indirect_baseHi;
+       uint32_t    disp_indirect_baseLo;
+       uint32_t    disp_indirect_baseHi;
+       uint32_t    gds_backup_addrlo;
+       uint32_t    gds_backup_addrhi;
+       uint32_t    index_base_addrlo;
+       uint32_t    index_base_addrhi;
+       uint32_t    sample_cntl;
+}; /* Total of 17 DWORD */
+
+struct amdgpu_ce_ib_state_chained_ib
+{
+       /* section of non chained ib part */
+       uint32_t    ce_ib_completion_status;
+       uint32_t    ce_constegnine_count;
+       uint32_t    ce_ibOffset_ib1;
+       uint32_t    ce_ibOffset_ib2;
+
+       /* section of chained ib */
+       uint32_t    ce_chainib_addrlo_ib1;
+       uint32_t    ce_chainib_addrlo_ib2;
+       uint32_t    ce_chainib_addrhi_ib1;
+       uint32_t    ce_chainib_addrhi_ib2;
+       uint32_t    ce_chainib_size_ib1;
+       uint32_t    ce_chainib_size_ib2;
+}; /* total 10 DWORD */
+
+struct amdgpu_de_ib_state_chained_ib
+{
+       /* section of non chained ib part */
+       uint32_t    ib_completion_status;
+       uint32_t    de_constEngine_count;
+       uint32_t    ib_offset_ib1;
+       uint32_t    ib_offset_ib2;
+
+       /* section of chained ib */
+       uint32_t    chain_ib_addrlo_ib1;
+       uint32_t    chain_ib_addrlo_ib2;
+       uint32_t    chain_ib_addrhi_ib1;
+       uint32_t    chain_ib_addrhi_ib2;
+       uint32_t    chain_ib_size_ib1;
+       uint32_t    chain_ib_size_ib2;
+
+       /* section of non chained ib part */
+       uint32_t    preamble_begin_ib1;
+       uint32_t    preamble_begin_ib2;
+       uint32_t    preamble_end_ib1;
+       uint32_t    preamble_end_ib2;
+
+       /* section of chained ib */
+       uint32_t    chain_ib_pream_addrlo_ib1;
+       uint32_t    chain_ib_pream_addrlo_ib2;
+       uint32_t    chain_ib_pream_addrhi_ib1;
+       uint32_t    chain_ib_pream_addrhi_ib2;
+
+       /* section of non chained ib part */
+       uint32_t    draw_indirect_baseLo;
+       uint32_t    draw_indirect_baseHi;
+       uint32_t    disp_indirect_baseLo;
+       uint32_t    disp_indirect_baseHi;
+       uint32_t    gds_backup_addrlo;
+       uint32_t    gds_backup_addrhi;
+       uint32_t    index_base_addrlo;
+       uint32_t    index_base_addrhi;
+       uint32_t    sample_cntl;
+}; /* Total of 27 DWORD */
+
+struct amdgpu_gfx_meta_data
+{
+       /* 4 DWORD, address must be 4KB aligned */
+       struct amdgpu_ce_ib_state    ce_payload;
+       uint32_t                     reserved1[60];
+       /* 17 DWORD, address must be 64B aligned */
+       struct amdgpu_de_ib_state    de_payload;
+       /* PFP IB base address which get pre-empted */
+       uint32_t                     DeIbBaseAddrLo;
+       uint32_t                     DeIbBaseAddrHi;
+       uint32_t                     reserved2[941];
+}; /* Total of 4K Bytes */
+
+struct amdgpu_gfx_meta_data_chained_ib
+{
+       /* 10 DWORD, address must be 4KB aligned */
+       struct amdgpu_ce_ib_state_chained_ib   ce_payload;
+       uint32_t                               reserved1[54];
+       /* 27 DWORD, address must be 64B aligned */
+       struct amdgpu_de_ib_state_chained_ib   de_payload;
+       /* PFP IB base address which get pre-empted */
+       uint32_t                               DeIbBaseAddrLo;
+       uint32_t                               DeIbBaseAddrHi;
+       uint32_t                               reserved2[931];
+}; /* Total of 4K Bytes */
+
 #endif