arm64: KVM: Add temporary kvm_perf_event.h

In order to merge the KVM/ARM PMU patches without creating a
conflict mess, let's have a temporary include file that won't
conflict with anything. Subsequent patches will clean that up.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 31fe7d6f32dedf3cdcd9b50905ed6f880da75d20..15851f52096b3a72b8a7733ad419334ceb674f47 100644 (file)
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -27,6 +27,7 @@
 #include <asm/kvm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
+#include <asm/kvm_perf_event.h>
 
 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
 

diff --git a/arch/arm64/include/asm/kvm_perf_event.h b/arch/arm64/include/asm/kvm_perf_event.h
new file mode 100644 (file)
index 0000000..d1c9d50
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_perf_event.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_KVM_PERF_EVENT_H
+#define __ASM_KVM_PERF_EVENT_H
+
+#define        ARMV8_PMU_MAX_COUNTERS  32
+#define        ARMV8_PMU_COUNTER_MASK  (ARMV8_PMU_MAX_COUNTERS - 1)
+
+/*
+ * Per-CPU PMCR: config reg
+ */
+#define ARMV8_PMU_PMCR_E       (1 << 0) /* Enable all counters */
+#define ARMV8_PMU_PMCR_P       (1 << 1) /* Reset all counters */
+#define ARMV8_PMU_PMCR_C       (1 << 2) /* Cycle counter reset */
+#define ARMV8_PMU_PMCR_D       (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV8_PMU_PMCR_X       (1 << 4) /* Export to ETM */
+#define ARMV8_PMU_PMCR_DP      (1 << 5) /* Disable CCNT if non-invasive debug*/
+#define        ARMV8_PMU_PMCR_N_SHIFT  11       /* Number of counters supported */
+#define        ARMV8_PMU_PMCR_N_MASK   0x1f
+#define        ARMV8_PMU_PMCR_MASK     0x3f     /* Mask for writable bits */
+
+/*
+ * PMOVSR: counters overflow flag status reg
+ */
+#define        ARMV8_PMU_OVSR_MASK             0xffffffff      /* Mask for writable bits */
+#define        ARMV8_PMU_OVERFLOWED_MASK       ARMV8_PMU_OVSR_MASK
+
+/*
+ * PMXEVTYPER: Event selection reg
+ */
+#define        ARMV8_PMU_EVTYPE_MASK   0xc80003ff      /* Mask for writable bits */
+#define        ARMV8_PMU_EVTYPE_EVENT  0x3ff           /* Mask for EVENT bits */
+
+/*
+ * Event filters for PMUv3
+ */
+#define        ARMV8_PMU_EXCLUDE_EL1   (1 << 31)
+#define        ARMV8_PMU_EXCLUDE_EL0   (1 << 30)
+#define        ARMV8_PMU_INCLUDE_EL2   (1 << 27)
+
+#endif