When HEVC encoding, the ROI is enabled at SEQ_START.
This adds to clear the ROI_ENABLE bit at SEQ_DONE.
Change-Id: If2ce5b25913915edbb8a7860232bdd71eeb028ba
Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
ctx->dpb_count = s5p_mfc_get_enc_dpb_count();
ctx->scratch_buf_size = s5p_mfc_get_enc_scratch_size();
+ /* If the ROI is enabled at SEQ_START, clear ROI_ENABLE bit */
+ s5p_mfc_clear_roi_enable(dev);
+
ret = s5p_mfc_alloc_codec_buffers(ctx);
if (ret) {
mfc_err_ctx("Failed to allocate encoding buffers.\n");
MFC_WRITEL(reg, S5P_FIMV_E_PARAM_CHANGE);
}
+static inline void s5p_mfc_clear_roi_enable(struct s5p_mfc_dev *dev)
+{
+ unsigned int reg = 0;
+
+ reg = MFC_READL(S5P_FIMV_E_RC_ROI_CTRL);
+ reg &= ~(0x1);
+ MFC_WRITEL(reg, S5P_FIMV_E_RC_ROI_CTRL);
+}
+
void s5p_mfc_dbg_enable(struct s5p_mfc_dev *dev);
void s5p_mfc_dbg_disable(struct s5p_mfc_dev *dev);
void s5p_mfc_dbg_set_addr(struct s5p_mfc_dev *dev);