ath9k_hw: Add few routines for rx edma support
authorVasanthakumar Thiagarajan <vasanth@atheros.com>
Thu, 15 Apr 2010 21:38:28 +0000 (17:38 -0400)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 16 Apr 2010 19:43:22 +0000 (15:43 -0400)
* Set rx buf size in register 0x60
* Set rxdp on the respective hw rx queue (HP and LP queues)
* Process rx descriptor

Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_mac.c
drivers/net/wireless/ath/ath9k/ar9003_mac.h
drivers/net/wireless/ath/ath9k/hw.h
drivers/net/wireless/ath/ath9k/mac.h
drivers/net/wireless/ath/ath9k/reg.h

index ee84e64b8b0c515352bcbcaa1415ce05bc322ab2..20890060ee2cb468d5c686d41543ecb36921b0a1 100644 (file)
@@ -26,3 +26,98 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
 
        ops->rx_enable = ar9003_hw_rx_enable;
 }
+
+void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
+{
+       REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
+}
+EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
+
+void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
+                           enum ath9k_rx_qtype qtype)
+{
+       if (qtype == ATH9K_RX_QUEUE_HP)
+               REG_WRITE(ah, AR_HP_RXDP, rxdp);
+       else
+               REG_WRITE(ah, AR_LP_RXDP, rxdp);
+}
+EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
+
+int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
+                                void *buf_addr)
+{
+       struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
+       unsigned int phyerr;
+
+       /* TODO: byte swap on big endian for ar9300_10 */
+
+       if ((rxsp->status11 & AR_RxDone) == 0)
+               return -EINPROGRESS;
+
+       if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
+               return -EINVAL;
+
+       if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
+               return -EINPROGRESS;
+
+       rxs->rs_status = 0;
+       rxs->rs_flags =  0;
+
+       rxs->rs_datalen = rxsp->status2 & AR_DataLen;
+       rxs->rs_tstamp =  rxsp->status3;
+
+       /* XXX: Keycache */
+       rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
+       rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
+       rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
+       rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
+       rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
+       rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
+       rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
+
+       if (rxsp->status11 & AR_RxKeyIdxValid)
+               rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
+       else
+               rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
+
+       rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
+       rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
+
+       rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
+       rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
+       rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
+       rxs->rs_flags  = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
+       rxs->rs_flags  |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
+
+       rxs->evm0 = rxsp->status6;
+       rxs->evm1 = rxsp->status7;
+       rxs->evm2 = rxsp->status8;
+       rxs->evm3 = rxsp->status9;
+       rxs->evm4 = (rxsp->status10 & 0xffff);
+
+       if (rxsp->status11 & AR_PreDelimCRCErr)
+               rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
+
+       if (rxsp->status11 & AR_PostDelimCRCErr)
+               rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
+
+       if (rxsp->status11 & AR_DecryptBusyErr)
+               rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
+
+       if ((rxsp->status11 & AR_RxFrameOK) == 0) {
+               if (rxsp->status11 & AR_CRCErr) {
+                       rxs->rs_status |= ATH9K_RXERR_CRC;
+               } else if (rxsp->status11 & AR_PHYErr) {
+                       rxs->rs_status |= ATH9K_RXERR_PHY;
+                       phyerr = MS(rxsp->status11, AR_PHYErrCode);
+                       rxs->rs_phyerr = phyerr;
+               } else if (rxsp->status11 & AR_DecryptCRCErr) {
+                       rxs->rs_status |= ATH9K_RXERR_DECRYPT;
+               } else if (rxsp->status11 & AR_MichaelErr) {
+                       rxs->rs_status |= ATH9K_RXERR_MIC;
+               }
+       }
+
+       return 0;
+}
+EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
index 2a9d80e9e0c7d14f9953b06bde22cdc686321e2f..b22f78c320c576b42dc98e5032e4b3fca63f68d8 100644 (file)
 #ifndef AR9003_MAC_H
 #define AR9003_MAC_H
 
+#define AR_DescId      0xffff0000
+#define AR_DescId_S    16
+#define AR_CtrlStat    0x00004000
+#define AR_TxRxDesc    0x00008000
+
 struct ar9003_rxs {
        u32 ds_info;
        u32 status1;
@@ -33,5 +38,12 @@ struct ar9003_rxs {
 } __packed;
 
 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
+void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
+void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
+                           enum ath9k_rx_qtype qtype);
+
+int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
+                                struct ath_rx_status *rxs,
+                                void *buf_addr);
 
 #endif
index b07ee8d6d33243c12904380f0fa1010414cd6bbc..d713ff2dfc551de9d0f8725ac29cdb36fbfd10e1 100644 (file)
@@ -370,6 +370,12 @@ enum ser_reg_mode {
        SER_REG_MODE_AUTO = 2,
 };
 
+enum ath9k_rx_qtype {
+       ATH9K_RX_QUEUE_HP,
+       ATH9K_RX_QUEUE_LP,
+       ATH9K_RX_QUEUE_MAX,
+};
+
 struct ath9k_beacon_state {
        u32 bs_nexttbtt;
        u32 bs_nextdtim;
index 9e8500a8c800f08993abc5ad73b636baedb41d22..126a4030be1d7dd7a65ffcb0372570e97f75883c 100644 (file)
@@ -148,6 +148,8 @@ struct ath_rx_status {
        u32 evm0;
        u32 evm1;
        u32 evm2;
+       u32 evm3;
+       u32 evm4;
 };
 
 struct ath_htc_rx_status {
index d524891491677a0e9df01b792f79d1220c7994bc..bc48bc92076fa172855d33c4f42f1416e4708e96 100644 (file)
 #define AR_MACMISC_MISC_OBS_BUS_MSB_S   15
 #define AR_MACMISC_MISC_OBS_BUS_1       1
 
+#define AR_DATABUF_SIZE                0x0060
+#define AR_DATABUF_SIZE_MASK   0x00000FFF
+
 #define AR_GTXTO    0x0064
 #define AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF
 #define AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000
 #define AR_CST_TIMEOUT_LIMIT      0xFFFF0000
 #define AR_CST_TIMEOUT_LIMIT_S    16
 
+#define AR_HP_RXDP 0x0074
+#define AR_LP_RXDP 0x0078
+
 #define AR_ISR               0x0080
 #define AR_ISR_RXOK          0x00000001
 #define AR_ISR_RXDESC        0x00000002