drm/rockchip/dsi: fix insufficient bandwidth of some panel

Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-7-git-send-email-zyw@rock-chips.com

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 1c7740ce052eeb3edfb9795bb7c4b38873bdc680..f4e21dab5f85f845bda8a73b3cd438621cfe5ba5 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -529,8 +529,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 
        mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
        if (mpclk) {
-               /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
-               tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
+               /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
+               tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
                if (tmp < max_mbps)
                        target_mbps = tmp;
                else