struct clk *adc_clk;
struct gpio_desc *xnur_gpio;
- int measure_delay_time;
- int pre_charge_time;
- int average_samples;
+ u32 measure_delay_time;
+ u32 pre_charge_time;
+ u32 average_samples;
struct completion completion;
};
*/
static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
{
- int adc_hc = 0;
- int adc_gc;
- int adc_gs;
- int adc_cfg;
- int timeout;
+ u32 adc_hc = 0;
+ u32 adc_gc;
+ u32 adc_gs;
+ u32 adc_cfg;
+ unsigned long timeout;
reinit_completion(&tsc->completion);
*/
static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
{
- int adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
+ u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
adc_hc0 = DISABLE_CONVERSION_INT;
writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
*/
static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
{
- int basic_setting = 0;
- int start;
+ u32 basic_setting = 0;
+ u32 start;
basic_setting |= tsc->measure_delay_time << 8;
basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE;
static void imx6ul_tsc_disable(struct imx6ul_tsc *tsc)
{
- int tsc_flow;
- int adc_cfg;
+ u32 tsc_flow;
+ u32 adc_cfg;
/* TSC controller enters to idle status */
tsc_flow = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
{
unsigned long timeout = jiffies + msecs_to_jiffies(2);
- int state_machine;
- int debug_mode2;
+ u32 state_machine;
+ u32 debug_mode2;
do {
if (time_after(jiffies, timeout))
static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
{
struct imx6ul_tsc *tsc = dev_id;
- int status;
- int value;
- int x, y;
- int start;
+ u32 status;
+ u32 value;
+ u32 x, y;
+ u32 start;
status = readl(tsc->tsc_regs + REG_TSC_INT_STATUS);
static irqreturn_t adc_irq_fn(int irq, void *dev_id)
{
struct imx6ul_tsc *tsc = dev_id;
- int coco;
- int value;
+ u32 coco;
+ u32 value;
coco = readl(tsc->adc_regs + REG_ADC_HS);
if (coco & 0x01) {