/* converts bits per word to CR0.DSS value */
#define bits_per_word_to_dss(bpw) ((bpw) - 1)
-static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
-{
- u32 val;
-
- val = readl(espi->mmio + SSPCR1);
- val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
- writel(val, espi->mmio + SSPCR1);
-}
-
-static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
-{
- u32 val;
-
- val = readl(espi->mmio + SSPCR1);
- val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
- writel(val, espi->mmio + SSPCR1);
-}
-
/**
* ep93xx_spi_calc_divisors() - calculates SPI clock divisors
* @espi: ep93xx SPI controller struct
* FIFO, enable interrupts, and wait for the transfer to complete.
*/
if (ep93xx_spi_read_write(espi)) {
- ep93xx_spi_enable_interrupts(espi);
+ u32 val;
+
+ val = readl(espi->mmio + SSPCR1);
+ val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
+ writel(val, espi->mmio + SSPCR1);
+
wait_for_completion(&espi->wait);
}
}
static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
{
struct ep93xx_spi *espi = dev_id;
+ u32 val;
/*
* If we got ROR (receive overrun) interrupt we know that something is
* any case we disable interrupts and notify the worker to handle
* any post-processing of the message.
*/
- ep93xx_spi_disable_interrupts(espi);
+ val = readl(espi->mmio + SSPCR1);
+ val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
+ writel(val, espi->mmio + SSPCR1);
+
complete(&espi->wait);
+
return IRQ_HANDLED;
}