#define NI_E_IRQ_FLAGS 0
-/* How we access registers */
-
-static uint8_t ni_atmio_inb(struct comedi_device *dev, int reg)
-{
- return inb(dev->iobase + reg);
-}
-
-static uint16_t ni_atmio_inw(struct comedi_device *dev, int reg)
-{
- return inw(dev->iobase + reg);
-}
-
-static uint32_t ni_atmio_inl(struct comedi_device *dev, int reg)
-{
- return inl(dev->iobase + reg);
-}
-
-static void ni_atmio_outb(struct comedi_device *dev, uint8_t val, int reg)
-{
- outb(val, dev->iobase + reg);
-}
-
-static void ni_atmio_outw(struct comedi_device *dev, uint16_t val, int reg)
-{
- outw(val, dev->iobase + reg);
-}
-
-static void ni_atmio_outl(struct comedi_device *dev, uint32_t val, int reg)
-{
- outl(val, dev->iobase + reg);
-}
+#include "ni_mio_common.c"
/* How we access windowed registers */
spin_lock_irqsave(&devpriv->window_lock, flags);
if ((addr) < 8) {
- devpriv->writew(dev, data, addr * 2);
+ ni_writew(dev, data, addr * 2);
} else {
- devpriv->writew(dev, addr, Window_Address);
- devpriv->writew(dev, data, Window_Data);
+ ni_writew(dev, addr, Window_Address);
+ ni_writew(dev, data, Window_Data);
}
spin_unlock_irqrestore(&devpriv->window_lock, flags);
}
spin_lock_irqsave(&devpriv->window_lock, flags);
if (addr < 8) {
- ret = devpriv->readw(dev, addr * 2);
+ ret = ni_readw(dev, addr * 2);
} else {
- devpriv->writew(dev, addr, Window_Address);
- ret = devpriv->readw(dev, Window_Data);
+ ni_writew(dev, addr, Window_Address);
+ ret = ni_readw(dev, Window_Data);
}
spin_unlock_irqrestore(&devpriv->window_lock, flags);
MODULE_DEVICE_TABLE(pnp, device_ids);
-#include "ni_mio_common.c"
-
static int ni_isapnp_find_board(struct pnp_dev **dev)
{
struct pnp_dev *isapnp_dev = NULL;
return ret;
devpriv = dev->private;
- devpriv->readb = ni_atmio_inb;
- devpriv->readw = ni_atmio_inw;
- devpriv->readl = ni_atmio_inl;
- devpriv->writeb = ni_atmio_outb;
- devpriv->writew = ni_atmio_outw;
- devpriv->writel = ni_atmio_outl;
-
devpriv->stc_writew = ni_atmio_win_out;
devpriv->stc_readw = ni_atmio_win_in;
devpriv->stc_writel = win_out2;
{
struct ni_private *devpriv = dev->private;
- devpriv->writel(dev, data, reg);
+ if (devpriv->mite)
+ writel(data, devpriv->mite->daq_io_addr + reg);
+ else
+ outl(data, dev->iobase + reg);
}
static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
{
struct ni_private *devpriv = dev->private;
- devpriv->writew(dev, data, reg);
+ if (devpriv->mite)
+ writew(data, devpriv->mite->daq_io_addr + reg);
+ else
+ outw(data, dev->iobase + reg);
}
static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
{
struct ni_private *devpriv = dev->private;
- devpriv->writeb(dev, data, reg);
+ if (devpriv->mite)
+ writeb(data, devpriv->mite->daq_io_addr + reg);
+ else
+ outb(data, dev->iobase + reg);
}
static uint32_t ni_readl(struct comedi_device *dev, int reg)
{
struct ni_private *devpriv = dev->private;
- return devpriv->readl(dev, reg);
+ if (devpriv->mite)
+ return readl(devpriv->mite->daq_io_addr + reg);
+ else
+ return inl(dev->iobase + reg);
}
static uint16_t ni_readw(struct comedi_device *dev, int reg)
{
struct ni_private *devpriv = dev->private;
- return devpriv->readw(dev, reg);
+ if (devpriv->mite)
+ return readw(devpriv->mite->daq_io_addr + reg);
+ else
+ return inw(dev->iobase + reg);
}
static uint8_t ni_readb(struct comedi_device *dev, int reg)
{
struct ni_private *devpriv = dev->private;
- return devpriv->readb(dev, reg);
+ if (devpriv->mite)
+ return readb(devpriv->mite->daq_io_addr + reg);
+ else
+ return inb(dev->iobase + reg);
}
static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
#define IRQ_POLARITY 1
-/* How we access registers */
-
-static uint8_t mio_cs_inb(struct comedi_device *dev, int reg)
-{
- return inb(dev->iobase + reg);
-}
-
-static uint16_t mio_cs_inw(struct comedi_device *dev, int reg)
-{
- return inw(dev->iobase + reg);
-}
-
-static uint32_t mio_cs_inl(struct comedi_device *dev, int reg)
-{
- return inl(dev->iobase + reg);
-}
-
-static void mio_cs_outb(struct comedi_device *dev, uint8_t val, int reg)
-{
- outb(val, dev->iobase + reg);
-}
-
-static void mio_cs_outw(struct comedi_device *dev, uint16_t val, int reg)
-{
- outw(val, dev->iobase + reg);
-}
-
-static void mio_cs_outl(struct comedi_device *dev, uint32_t val, int reg)
-{
- outl(val, dev->iobase + reg);
-}
+#include "ni_mio_common.c"
/* How we access windowed registers */
spin_lock_irqsave(&devpriv->window_lock, flags);
if (addr < 8) {
- devpriv->writew(dev, data, addr * 2);
+ ni_writew(dev, data, addr * 2);
} else {
- devpriv->writew(dev, addr, Window_Address);
- devpriv->writew(dev, data, Window_Data);
+ ni_writew(dev, addr, Window_Address);
+ ni_writew(dev, data, Window_Data);
}
spin_unlock_irqrestore(&devpriv->window_lock, flags);
}
spin_lock_irqsave(&devpriv->window_lock, flags);
if (addr < 8) {
- ret = devpriv->readw(dev, addr * 2);
+ ret = ni_readw(dev, addr * 2);
} else {
- devpriv->writew(dev, addr, Window_Address);
- ret = devpriv->readw(dev, Window_Data);
+ ni_writew(dev, addr, Window_Address);
+ ret = ni_readw(dev, Window_Data);
}
spin_unlock_irqrestore(&devpriv->window_lock, flags);
return ret;
}
-#include "ni_mio_common.c"
-
static const void *ni_getboardtype(struct comedi_device *dev,
struct pcmcia_device *link)
{
devpriv = dev->private;
- devpriv->readb = mio_cs_inb;
- devpriv->readw = mio_cs_inw;
- devpriv->readl = mio_cs_inl;
- devpriv->writeb = mio_cs_outb;
- devpriv->writew = mio_cs_outw;
- devpriv->writel = mio_cs_outl;
-
devpriv->stc_writew = mio_cs_win_out;
devpriv->stc_readw = mio_cs_win_in;
devpriv->stc_writel = win_out2;
},
};
-/* How we access registers */
-
-static uint8_t pcimio_readb(struct comedi_device *dev, int reg)
-{
- struct ni_private *devpriv = dev->private;
-
- return readb(devpriv->mite->daq_io_addr + reg);
-}
-
-static uint16_t pcimio_readw(struct comedi_device *dev, int reg)
-{
- struct ni_private *devpriv = dev->private;
-
- return readw(devpriv->mite->daq_io_addr + reg);
-}
-
-static uint32_t pcimio_readl(struct comedi_device *dev, int reg)
-{
- struct ni_private *devpriv = dev->private;
-
- return readl(devpriv->mite->daq_io_addr + reg);
-}
-
-static void pcimio_writeb(struct comedi_device *dev, uint8_t val, int reg)
-{
- struct ni_private *devpriv = dev->private;
-
- writeb(val, devpriv->mite->daq_io_addr + reg);
-}
-
-static void pcimio_writew(struct comedi_device *dev, uint16_t val, int reg)
-{
- struct ni_private *devpriv = dev->private;
-
- writew(val, devpriv->mite->daq_io_addr + reg);
-}
+#define interrupt_pin(a) 0
+#define IRQ_POLARITY 1
-static void pcimio_writel(struct comedi_device *dev, uint32_t val, int reg)
-{
- struct ni_private *devpriv = dev->private;
+#define NI_E_IRQ_FLAGS IRQF_SHARED
- writel(val, devpriv->mite->daq_io_addr + reg);
-}
+#include "ni_mio_common.c"
/* How we access STC registers */
unsigned long flags;
spin_lock_irqsave(&devpriv->window_lock, flags);
- devpriv->writew(dev, reg, Window_Address);
- devpriv->writew(dev, data, Window_Data);
+ ni_writew(dev, reg, Window_Address);
+ ni_writew(dev, data, Window_Data);
spin_unlock_irqrestore(&devpriv->window_lock, flags);
}
uint16_t ret;
spin_lock_irqsave(&devpriv->window_lock, flags);
- devpriv->writew(dev, reg, Window_Address);
- ret = devpriv->readw(dev, Window_Data);
+ ni_writew(dev, reg, Window_Address);
+ ret = ni_readw(dev, Window_Data);
spin_unlock_irqrestore(&devpriv->window_lock, flags);
return ret;
static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
int reg)
{
- struct ni_private *devpriv = dev->private;
unsigned offset;
switch (reg) {
break;
case AI_SI2_Load_A_Register:
/* this is actually a 32 bit register on m series boards */
- devpriv->writel(dev, data, M_Offset_AI_SI2_Load_A);
+ ni_writel(dev, data, M_Offset_AI_SI2_Load_A);
return;
break;
case AI_SI2_Load_B_Register:
/* this is actually a 32 bit register on m series boards */
- devpriv->writel(dev, data, M_Offset_AI_SI2_Load_B);
+ ni_writel(dev, data, M_Offset_AI_SI2_Load_B);
return;
break;
case AI_START_STOP_Select_Register:
return;
break;
}
- devpriv->writew(dev, data, offset);
+ ni_writew(dev, data, offset);
}
static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
{
- struct ni_private *devpriv = dev->private;
unsigned offset;
switch (reg) {
offset = M_Offset_AO_Status_2;
break;
case DIO_Serial_Input_Register:
- return devpriv->readb(dev, M_Offset_SCXI_Serial_Data_In);
+ return ni_readb(dev, M_Offset_SCXI_Serial_Data_In);
break;
case Joint_Status_1_Register:
offset = M_Offset_Joint_Status_1;
return 0;
break;
}
- return devpriv->readw(dev, offset);
+ return ni_readw(dev, offset);
}
static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
int reg)
{
- struct ni_private *devpriv = dev->private;
unsigned offset;
switch (reg) {
return;
break;
}
- devpriv->writel(dev, data, offset);
+ ni_writel(dev, data, offset);
}
static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
{
- struct ni_private *devpriv = dev->private;
unsigned offset;
switch (reg) {
return 0;
break;
}
- return devpriv->readl(dev, offset);
+ return ni_readl(dev, offset);
}
-#define interrupt_pin(a) 0
-#define IRQ_POLARITY 1
-
-#define NI_E_IRQ_FLAGS IRQF_SHARED
-
-#include "ni_mio_common.c"
-
static int pcimio_ai_change(struct comedi_device *dev,
struct comedi_subdevice *s, unsigned long new_size);
static int pcimio_ao_change(struct comedi_device *dev,
BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
for (i = 0; i < serial_number_eeprom_length; ++i) {
char *byte_ptr = (char *)&devpriv->serial_number + i;
- *byte_ptr = devpriv->readb(dev,
- serial_number_eeprom_offset + i);
+ *byte_ptr = ni_readb(dev, serial_number_eeprom_offset + i);
}
devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
- devpriv->eeprom_buffer[i] = devpriv->readb(dev,
- Start_Cal_EEPROM + i);
+ devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
/* Initialise 6143 AI specific bits */
/* Set G0,G1 DMA mode to E series version */
- devpriv->writeb(dev, 0x00, Magic_6143);
+ ni_writeb(dev, 0x00, Magic_6143);
/* Set EOCMode, ADCMode and pipelinedelay */
- devpriv->writeb(dev, 0x80, PipelineDelay_6143);
+ ni_writeb(dev, 0x80, PipelineDelay_6143);
/* Set EOC Delay */
- devpriv->writeb(dev, 0x00, EOC_Set_6143);
+ ni_writeb(dev, 0x00, EOC_Set_6143);
/* Set the FIFO half full level */
- devpriv->writel(dev, board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
+ ni_writel(dev, board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
/* Strobe Relay disable bit */
devpriv->ai_calib_source_enabled = 0;
- devpriv->writew(dev, devpriv->ai_calib_source |
- Calibration_Channel_6143_RelayOff,
- Calibration_Channel_6143);
- devpriv->writew(dev, devpriv->ai_calib_source,
- Calibration_Channel_6143);
+ ni_writew(dev, devpriv->ai_calib_source |
+ Calibration_Channel_6143_RelayOff,
+ Calibration_Channel_6143);
+ ni_writew(dev, devpriv->ai_calib_source, Calibration_Channel_6143);
}
static void pcimio_detach(struct comedi_device *dev)
if (!devpriv->mite)
return -ENOMEM;
- devpriv->readb = pcimio_readb;
- devpriv->readw = pcimio_readw;
- devpriv->readl = pcimio_readl;
- devpriv->writeb = pcimio_writeb;
- devpriv->writew = pcimio_writew;
- devpriv->writel = pcimio_writel;
-
if (board->reg_type & ni_reg_m_series_mask) {
devpriv->is_m_series = 1;
#define NUM_GPCT 2
struct ni_private {
- uint8_t (*readb)(struct comedi_device *, int reg);
- uint16_t (*readw)(struct comedi_device *, int reg);
- uint32_t (*readl)(struct comedi_device *, int reg);
- void (*writeb)(struct comedi_device *, uint8_t value, int reg);
- void (*writew)(struct comedi_device *, uint16_t value, int reg);
- void (*writel)(struct comedi_device *, uint32_t value, int reg);
-
uint16_t (*stc_readw)(struct comedi_device *, int reg);
uint32_t (*stc_readl)(struct comedi_device *, int reg);
void (*stc_writew)(struct comedi_device *, uint16_t value, int reg);