Calculation of the CLKDIV speed setting should be done using base 10 math
rather than base 2. We also avoid exceeding the spec due to integer
truncation and a 50% duty cycle.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
}
/* Set TWI internal clock as 10MHz */
- write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
+ write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
/*
* We will not end up with a CLKDIV=0 because no one will specify
- * 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100)
+ * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
*/
- clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ;
+ clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
/* Set Twi interface clock as specified */
write_CLKDIV(iface, (clkhilow << 8) | clkhilow);