* IOP13XX chipset registers
*/
#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
-#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
-#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
- (IOP13XX_PMMR_PHYS_MEM_BASE\
- - IOP13XX_PMMR_VIRT_MEM_BASE))
-#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
- (IOP13XX_PMMR_PHYS_MEM_BASE\
- - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
+ + IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
+ + IOP13XX_PMMR_VIRT_MEM_BASE)
#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_PMMR_SIZE 0x00080000
/*=================== Defines for Platform Devices =====================*/
-#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
-#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
+#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
-static inline dma_addr_t __virt_to_lbus(unsigned long x)
+static inline dma_addr_t __virt_to_lbus(void __iomem *x)
{
return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
}
-static inline unsigned long __lbus_to_virt(dma_addr_t x)
+static inline void __iomem *__lbus_to_virt(dma_addr_t x)
{
return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
}
#define __arch_dma_to_virt(dev, addr) \
({ \
- unsigned long __virt; \
+ void * __virt; \
dma_addr_t __dma = addr; \
if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
__virt = __lbus_to_virt(__dma); \
else \
- __virt = __phys_to_virt(__dma); \
- (void *)__virt; \
+ __virt = (void *)__phys_to_virt(__dma); \
+ __virt; \
})
#define __arch_virt_to_dma(dev, addr) \
({ \
- unsigned long __virt = (unsigned long)addr; \
+ void * __virt = addr; \
dma_addr_t __dma; \
if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
__dma = __virt_to_lbus(__virt); \
else \
- __dma = __virt_to_phys(__virt); \
+ __dma = __virt_to_phys((unsigned long)__virt); \
__dma; \
})
if (unlikely(!iop13xx_atux_mem_base))
retval = NULL;
else
- retval = (void *)(iop13xx_atux_mem_base +
+ retval = (iop13xx_atux_mem_base +
(cookie - IOP13XX_PCIX_LOWER_MEM_RA));
break;
case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
if (unlikely(!iop13xx_atue_mem_base))
retval = NULL;
else
- retval = (void *)(iop13xx_atue_mem_base +
+ retval = (iop13xx_atue_mem_base +
(cookie - IOP13XX_PCIE_LOWER_MEM_RA));
break;
case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
break;
case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
- retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+ retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
break;
default:
retval = __arm_ioremap_caller(cookie, size, mtype,
goto skip;
switch ((u32) addr) {
- case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
- case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
- case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
+ case (u32)IOP13XX_PCIE_LOWER_IO_VA ... (u32)IOP13XX_PCIE_UPPER_IO_VA:
+ case (u32)IOP13XX_PCIX_LOWER_IO_VA ... (u32)IOP13XX_PCIX_UPPER_IO_VA:
+ case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
goto skip;
}
__iounmap(addr);
u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
static struct pci_bus *pci_bus_atux = 0;
static struct pci_bus *pci_bus_atue = 0;
-u32 iop13xx_atue_mem_base;
-u32 iop13xx_atux_mem_base;
+void __iomem *iop13xx_atue_mem_base;
+void __iomem *iop13xx_atux_mem_base;
size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size;
}
if (end) {
- iop13xx_atux_mem_base =
- (u32) __arm_ioremap_pfn(
+ iop13xx_atux_mem_base = __arm_ioremap_pfn(
__phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
, 0, iop13xx_atux_mem_size, MT_DEVICE);
if (!iop13xx_atux_mem_base) {
}
} else
iop13xx_atux_mem_size = 0;
- PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+ PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
__func__, atu, iop13xx_atux_mem_size,
iop13xx_atux_mem_base);
break;
}
if (end) {
- iop13xx_atue_mem_base =
- (u32) __arm_ioremap_pfn(
+ iop13xx_atue_mem_base = __arm_ioremap_pfn(
__phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
, 0, iop13xx_atue_mem_size, MT_DEVICE);
if (!iop13xx_atue_mem_base) {
}
} else
iop13xx_atue_mem_size = 0;
- PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+ PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
__func__, atu, iop13xx_atue_mem_size,
iop13xx_atue_mem_base);
break;
}
- printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+ printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
atu ? "ATUE" : "ATUX",
(atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
SZ_1M,
#include <linux/types.h>
-extern u32 iop13xx_atue_mem_base;
-extern u32 iop13xx_atux_mem_base;
+extern void __iomem *iop13xx_atue_mem_base;
+extern void __iomem *iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;
*/
static struct map_desc iop13xx_std_desc[] __initdata = {
{ /* mem mapped registers */
- .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+ .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
.length = IOP13XX_PMMR_SIZE,
.type = MT_DEVICE,
static struct plat_serial8250_port iop13xx_uart0_data[] = {
{
- .membase = (char*)(IOP13XX_UART0_VIRT),
- .mapbase = (IOP13XX_UART0_PHYS),
+ .membase = IOP13XX_UART0_VIRT,
+ .mapbase = IOP13XX_UART0_PHYS,
.irq = IRQ_IOP13XX_UART0,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,
static struct plat_serial8250_port iop13xx_uart1_data[] = {
{
- .membase = (char*)(IOP13XX_UART1_VIRT),
- .mapbase = (IOP13XX_UART1_PHYS),
+ .membase = IOP13XX_UART1_VIRT,
+ .mapbase = IOP13XX_UART1_PHYS,
.irq = IRQ_IOP13XX_UART1,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,