struct device_node *iommu;
struct device_node *hwfc;
struct device_node *mmcache;
+ struct device_node *cmu = NULL;
struct resource *res;
int ret;
} else {
dev->has_mmcache = 1;
}
+
+ cmu = of_get_child_by_name(np, "cmu");
+ if (cmu) {
+ dev->cmu_busc_base = of_iomap(cmu, 0);
+ if (dev->cmu_busc_base == NULL) {
+ dev_err(&pdev->dev, "failed to iomap busc address region\n");
+ goto err_ioremap_cmu_busc;
+ }
+ dev->cmu_mif0_base = of_iomap(cmu, 1);
+ if (dev->cmu_mif0_base == NULL) {
+ dev_err(&pdev->dev, "failed to iomap mif0 address region\n");
+ goto err_ioremap_cmu_mif0;
+ }
+ dev->cmu_mif1_base = of_iomap(cmu, 2);
+ if (dev->cmu_mif1_base == NULL) {
+ dev_err(&pdev->dev, "failed to iomap mif1 address region\n");
+ goto err_ioremap_cmu_mif1;
+ }
+ dev->cmu_mif2_base = of_iomap(cmu, 3);
+ if (dev->cmu_mif2_base == NULL) {
+ dev_err(&pdev->dev, "failed to iomap mif2 address region\n");
+ goto err_ioremap_cmu_mif2;
+ }
+ dev->cmu_mif3_base = of_iomap(cmu, 4);
+ if (dev->cmu_mif3_base == NULL) {
+ dev_err(&pdev->dev, "failed to iomap mif3 address region\n");
+ goto err_ioremap_cmu_mif3;
+ }
+ dev->has_cmu = 1;
+ }
}
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
return 0;
err_res_irq:
+ if (cmu)
+ iounmap(dev->cmu_mif3_base);
+err_ioremap_cmu_mif3:
+ if (cmu)
+ iounmap(dev->cmu_mif2_base);
+err_ioremap_cmu_mif2:
+ if (cmu)
+ iounmap(dev->cmu_mif1_base);
+err_ioremap_cmu_mif1:
+ if (cmu)
+ iounmap(dev->cmu_mif0_base);
+err_ioremap_cmu_mif0:
+ if (cmu)
+ iounmap(dev->cmu_busc_base);
+err_ioremap_cmu_busc:
if (dev->has_mmcache)
iounmap(dev->mmcache.base);
err_ioremap_mmcache:
mfc_debug_leave();
}
+void __mfc_mmcache_dump_info(struct mfc_dev *dev)
+{
+ pr_err("-----------dumping MMCACHE registers (SFR base = 0x%#lx, dev = 0x%pK)\n",
+ (unsigned long)dev->mmcache.base, dev);
+ print_hex_dump(KERN_ERR, "[MMCACHE] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->mmcache.base, 0x10, false);
+
+ if (dev->has_cmu) {
+ pr_err("-----------dumping CMU BUSC registers (SFR base = 0x%#lx, dev = 0x%pK)\n",
+ (unsigned long)dev->cmu_busc_base, dev);
+ /* PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER (0x140) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][BUSC] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_busc_base + 0x140, 0xc, false);
+ /* CMU_BUSC (0x60ec) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][BUSC] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_busc_base + 0x60e0, 0x10, false);
+ /* DBG_NFO_QCH_CON_MMCACHE_QCH (0x7184) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][BUSC] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_busc_base + 0x7180, 0x10, false);
+
+ pr_err("-----------dumping CMU MIF0~3 registers (SFR base = 0x%#lx, dev = 0x%pK)\n",
+ (unsigned long)dev->cmu_mif0_base, dev);
+ /* CMU_MIF0 (0x7018 ~ 0x7024) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][MIF0] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_mif0_base + 0x7018, 0x10, false);
+ /* CMU_MIF1 (0x7018 ~ 0x7024) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][MIF1] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_mif1_base + 0x7018, 0x10, false);
+ /* CMU_MIF2 (0x7018 ~ 0x7024) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][MIF2] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_mif2_base + 0x7018, 0x10, false);
+ /* CMU_MIF3 (0x7018 ~ 0x7024) */
+ print_hex_dump(KERN_ERR, "[MMCACHE][MIF3] ", DUMP_PREFIX_ADDRESS, 32, 4, dev->cmu_mif3_base + 0x7018, 0x10, false);
+ }
+}
+
void mfc_invalidate_mmcache(struct mfc_dev *dev)
{
int ret;
/* The secure OS can flush all normal and secure data */
ret = exynos_smc(SMC_CMD_MM_CACHE_OPERATION, MMCACHE_GROUP2, 0x0, 0x0);
if (ret != DRMDRV_OK) {
- mfc_err_dev("[MMCACHE] Fail to invalidation %x\n", ret);
+ mfc_err_dev("[MMCACHE] Fail to invalidation 0x%x\n", ret);
+ __mfc_mmcache_dump_info(dev);
call_dop(dev, dump_and_stop_debug_mode, dev);
}
-
mfc_debug(2, "[MMCACHE] invalidated\n");
MFC_TRACE_DEV("[MMCACHE] invalidated\n");